mirror of
https://github.com/tbsdtv/linux_media.git
synced 2025-07-22 20:30:58 +02:00
2994bf7705
Update the PP2 ethernet ports subnodes' names to match
schema enforced by the marvell,pp2.yaml contents.
Add new required properties ('reg') which contains information
about the port ID, keeping 'port-id' ones for backward
compatibility.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
603 lines
16 KiB
Plaintext
603 lines
16 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
|
*
|
|
* Device Tree file for Marvell Armada CP11x.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
|
|
#include <dt-bindings/thermal/thermal.h>
|
|
|
|
#include "armada-common.dtsi"
|
|
|
|
#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
|
|
|
|
/ {
|
|
/*
|
|
* The contents of the node are defined below, in order to
|
|
* save one indentation level
|
|
*/
|
|
CP11X_NAME: CP11X_NAME { };
|
|
|
|
/*
|
|
* CPs only have one sensor in the thermal IC.
|
|
*
|
|
* The cooling maps are empty as there are no cooling devices.
|
|
*/
|
|
thermal-zones {
|
|
CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
|
|
polling-delay-passive = <0>; /* Interrupt driven */
|
|
polling-delay = <0>; /* Interrupt driven */
|
|
|
|
thermal-sensors = <&CP11X_LABEL(thermal) 0>;
|
|
|
|
trips {
|
|
CP11X_LABEL(crit): crit {
|
|
temperature = <100000>; /* mC degrees */
|
|
hysteresis = <2000>; /* mC degrees */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps { };
|
|
};
|
|
};
|
|
};
|
|
|
|
&CP11X_NAME {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
|
|
ranges;
|
|
|
|
config-space@CP11X_BASE {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
|
|
|
|
CP11X_LABEL(ethernet): ethernet@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,armada-7k-pp22";
|
|
reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
|
|
clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
|
|
<&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
|
|
<&CP11X_LABEL(clk) 1 18>;
|
|
clock-names = "pp_clk", "gop_clk",
|
|
"mg_clk", "mg_core_clk", "axi_clk";
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
status = "disabled";
|
|
dma-coherent;
|
|
|
|
CP11X_LABEL(eth0): ethernet-port@0 {
|
|
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<63 IRQ_TYPE_LEVEL_HIGH>,
|
|
<67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<129 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hif0", "hif1", "hif2",
|
|
"hif3", "hif4", "hif5", "hif6", "hif7",
|
|
"hif8", "link";
|
|
reg = <0>;
|
|
port-id = <0>; /* For backward compatibility. */
|
|
gop-port-id = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(eth1): ethernet-port@1 {
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<128 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hif0", "hif1", "hif2",
|
|
"hif3", "hif4", "hif5", "hif6", "hif7",
|
|
"hif8", "link";
|
|
reg = <1>;
|
|
port-id = <1>; /* For backward compatibility. */
|
|
gop-port-id = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(eth2): ethernet-port@2 {
|
|
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<127 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hif0", "hif1", "hif2",
|
|
"hif3", "hif4", "hif5", "hif6", "hif7",
|
|
"hif8", "link";
|
|
reg = <2>;
|
|
port-id = <2>; /* For backward compatibility. */
|
|
gop-port-id = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(comphy): phy@120000 {
|
|
compatible = "marvell,comphy-cp110";
|
|
reg = <0x120000 0x6000>;
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
|
|
<&CP11X_LABEL(clk) 1 18>;
|
|
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
CP11X_LABEL(comphy0): phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
CP11X_LABEL(comphy1): phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
CP11X_LABEL(comphy2): phy@2 {
|
|
reg = <2>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
CP11X_LABEL(comphy3): phy@3 {
|
|
reg = <3>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
CP11X_LABEL(comphy4): phy@4 {
|
|
reg = <4>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
CP11X_LABEL(comphy5): phy@5 {
|
|
reg = <5>;
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(mdio): mdio@12a200 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,orion-mdio";
|
|
reg = <0x12a200 0x10>;
|
|
clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
|
|
<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(xmdio): mdio@12a600 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,xmdio";
|
|
reg = <0x12a600 0x10>;
|
|
clocks = <&CP11X_LABEL(clk) 1 5>,
|
|
<&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(icu): interrupt-controller@1e0000 {
|
|
compatible = "marvell,cp110-icu";
|
|
reg = <0x1e0000 0x440>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
CP11X_LABEL(icu_nsr): interrupt-controller@10 {
|
|
compatible = "marvell,cp110-icu-nsr";
|
|
reg = <0x10 0x20>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
msi-parent = <&gicp>;
|
|
};
|
|
|
|
CP11X_LABEL(icu_sei): interrupt-controller@50 {
|
|
compatible = "marvell,cp110-icu-sei";
|
|
reg = <0x50 0x10>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
msi-parent = <&sei>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(rtc): rtc@284000 {
|
|
compatible = "marvell,armada-8k-rtc";
|
|
reg = <0x284000 0x20>, <0x284080 0x24>;
|
|
reg-names = "rtc", "rtc-soc";
|
|
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
CP11X_LABEL(syscon0): system-controller@440000 {
|
|
compatible = "syscon", "simple-mfd";
|
|
reg = <0x440000 0x2000>;
|
|
|
|
CP11X_LABEL(clk): clock {
|
|
compatible = "marvell,cp110-clock";
|
|
#clock-cells = <2>;
|
|
};
|
|
|
|
CP11X_LABEL(gpio1): gpio@100 {
|
|
compatible = "marvell,armada-8k-gpio";
|
|
offset = <0x100>;
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
|
|
marvell,pwm-offset = <0x1f0>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<83 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(gpio2): gpio@140 {
|
|
compatible = "marvell,armada-8k-gpio";
|
|
offset = <0x140>;
|
|
ngpios = <31>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
|
|
marvell,pwm-offset = <0x1f0>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<80 IRQ_TYPE_LEVEL_HIGH>,
|
|
<79 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(syscon1): system-controller@400000 {
|
|
compatible = "syscon", "simple-mfd";
|
|
reg = <0x400000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
CP11X_LABEL(thermal): thermal-sensor@70 {
|
|
compatible = "marvell,armada-cp110-thermal";
|
|
reg = <0x70 0x10>;
|
|
interrupts-extended =
|
|
<&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(utmi): utmi@580000 {
|
|
compatible = "marvell,cp110-utmi-phy";
|
|
reg = <0x580000 0x2000>;
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
CP11X_LABEL(utmi0): usb-phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
CP11X_LABEL(utmi1): usb-phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(usb3_0): usb@500000 {
|
|
compatible = "marvell,armada-8k-xhci",
|
|
"generic-xhci";
|
|
reg = <0x500000 0x4000>;
|
|
dma-coherent;
|
|
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 22>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(usb3_1): usb@510000 {
|
|
compatible = "marvell,armada-8k-xhci",
|
|
"generic-xhci";
|
|
reg = <0x510000 0x4000>;
|
|
dma-coherent;
|
|
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 23>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(sata0): sata@540000 {
|
|
compatible = "marvell,armada-8k-ahci",
|
|
"generic-ahci";
|
|
reg = <0x540000 0x30000>;
|
|
dma-coherent;
|
|
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&CP11X_LABEL(clk) 1 15>,
|
|
<&CP11X_LABEL(clk) 1 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sata-port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
sata-port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(xor0): xor@6a0000 {
|
|
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
|
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 8>,
|
|
<&CP11X_LABEL(clk) 1 14>;
|
|
};
|
|
|
|
CP11X_LABEL(xor1): xor@6c0000 {
|
|
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
|
reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 7>,
|
|
<&CP11X_LABEL(clk) 1 14>;
|
|
};
|
|
|
|
CP11X_LABEL(spi0): spi@700600 {
|
|
compatible = "marvell,armada-380-spi";
|
|
reg = <0x700600 0x50>;
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(spi1): spi@700680 {
|
|
compatible = "marvell,armada-380-spi";
|
|
reg = <0x700680 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(i2c0): i2c@701000 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x701000 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(i2c1): i2c@701100 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x701100 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart0): serial@702000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702000 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart1): serial@702100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702100 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart2): serial@702200 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(uart3): serial@702300 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x702300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
clocks = <&CP11X_LABEL(clk) 1 21>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(nand_controller): nand@720000 {
|
|
/*
|
|
* Due to the limitation of the pins available
|
|
* this controller is only usable on the CPM
|
|
* for A7K and on the CPS for A8K.
|
|
*/
|
|
compatible = "marvell,armada-8k-nand-controller",
|
|
"marvell,armada370-nand-controller";
|
|
reg = <0x720000 0x54>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 2>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(trng): trng@760000 {
|
|
compatible = "marvell,armada-8k-rng",
|
|
"inside-secure,safexcel-eip76";
|
|
reg = <0x760000 0x7d>;
|
|
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 25>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
status = "okay";
|
|
};
|
|
|
|
CP11X_LABEL(sdhci0): mmc@780000 {
|
|
compatible = "marvell,armada-cp110-sdhci";
|
|
reg = <0x780000 0x300>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "axi";
|
|
clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(crypto): crypto@800000 {
|
|
compatible = "inside-secure,safexcel-eip197b";
|
|
reg = <0x800000 0x200000>;
|
|
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<92 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mem", "ring0", "ring1",
|
|
"ring2", "ring3", "eip";
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 26>,
|
|
<&CP11X_LABEL(clk) 1 17>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
|
|
<0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
/* non-prefetchable memory */
|
|
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
};
|