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4e748b1bd7
Now that we actually read registers from QSGMII PCSs, it's important that we have the correct address (instead of hoping that we're the MAC with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII PCSs. The exact mapping of QSGMII to MACs depends on the SoC. Since the first QSGMII PCSs share an address with the SGMII and XFI PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts on the bus. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
74 lines
1.4 KiB
Plaintext
74 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 device tree nodes for ls1046
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*
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* Copyright 2015-2016 Freescale Semiconductor Inc.
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*
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*/
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&soc {
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/* include used FMan blocks */
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#include "qoriq-fman3-0.dtsi"
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#include "qoriq-fman3-0-1g-0.dtsi"
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#include "qoriq-fman3-0-1g-1.dtsi"
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#include "qoriq-fman3-0-1g-2.dtsi"
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#include "qoriq-fman3-0-1g-3.dtsi"
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#include "qoriq-fman3-0-1g-4.dtsi"
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#include "qoriq-fman3-0-1g-5.dtsi"
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#include "qoriq-fman3-0-10g-0.dtsi"
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#include "qoriq-fman3-0-10g-1.dtsi"
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};
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&fman0 {
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/* these aliases provide the FMan ports mapping */
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enet0: ethernet@e0000 {
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pcsphy-handle = <&qsgmiib_pcs3>;
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pcs-handle-names = "qsgmii";
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};
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enet1: ethernet@e2000 {
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};
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enet2: ethernet@e4000 {
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};
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enet3: ethernet@e6000 {
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};
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enet4: ethernet@e8000 {
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pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
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pcs-handle-names = "sgmii", "qsgmii";
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};
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enet5: ethernet@ea000 {
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pcsphy-handle = <&pcsphy5>, <&pcsphy5>;
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pcs-handle-names = "sgmii", "qsgmii";
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};
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enet6: ethernet@f0000 {
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};
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enet7: ethernet@f2000 {
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pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
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pcs-handle-names = "sgmii", "qsgmii", "xfi";
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};
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mdio@eb000 {
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qsgmiib_pcs1: ethernet-pcs@1 {
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compatible = "fsl,lynx-pcs";
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reg = <0x1>;
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};
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qsgmiib_pcs2: ethernet-pcs@2 {
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compatible = "fsl,lynx-pcs";
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reg = <0x2>;
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};
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qsgmiib_pcs3: ethernet-pcs@3 {
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compatible = "fsl,lynx-pcs";
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reg = <0x3>;
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};
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};
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};
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