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fpga: dfl-pci: locate DFLs by PCIe vendor specific capability

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A PCIe vendor specific extended capability is introduced by Intel to
specify the start of a number of DFLs.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-3-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matthew Gerlach
2021-01-06 20:37:08 -08:00
committed by Greg Kroah-Hartman
parent 3e265f836e
commit fa41d10589
2 changed files with 113 additions and 1 deletions
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27
Documentation/fpga/dfl.rst
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@@ -501,6 +501,33 @@ Developer only needs to provide a sub feature driver with matched feature id.
FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
could be a reference.
Location of DFLs on a PCI Device
===========================
The original method for finding a DFL on a PCI device assumed the start of the
first DFL to offset 0 of bar 0. If the first node of the DFL is an FME,
then further DFLs in the port(s) are specified in FME header registers.
Alternatively, a PCIe vendor specific capability structure can be used to
specify the location of all the DFLs on the device, providing flexibility
for the type of starting node in the DFL. Intel has reserved the
VSEC ID of 0x43 for this purpose. The vendor specific
data begins with a 4 byte vendor specific register for the number of DFLs followed 4 byte
Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register
indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are
zero.
+----------------------------+
|31 Number of DFLS 0|
+----------------------------+
|31 Offset 3|2 BIR 0|
+----------------------------+
. . .
+----------------------------+
|31 Offset 3|2 BIR 0|
+----------------------------+
Being able to specify more than one DFL per BAR has been considered, but it
was determined the use case did not provide value. Specifying a single DFL
per BAR simplifies the implementation and allows for extra error checking.
Open discussion
===============