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crypto: sun8i-ce - Add TRNG clock to the D1 variant

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At least the D1 variant requires a separate clock for the TRNG.
Without this clock enabled, reading from /dev/hwrng reports:

   sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3

Experimentation shows that the necessary clock is the SoC's internal
RC oscillator. This makes sense, as noise from the oscillator can be
used as a source of entropy.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Samuel Holland
2022-12-31 16:01:44 -06:00
committed by Herbert Xu
parent 197286f860
commit f81c1d4a6d
2 changed files with 2 additions and 1 deletions
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1
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
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@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_variant = {
{ "bus", 0, 200000000 }, { "bus", 0, 200000000 },
{ "mod", 300000000, 0 }, { "mod", 300000000, 0 },
{ "ram", 0, 400000000 }, { "ram", 0, 400000000 },
{ "trng", 0, 0 },
}, },
.esr = ESR_D1, .esr = ESR_D1,
.prng = CE_ALG_PRNG, .prng = CE_ALG_PRNG,

2
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
View File

@@ -105,7 +105,7 @@
#define MAX_SG 8 #define MAX_SG 8
#define CE_MAX_CLOCKS 3 #define CE_MAX_CLOCKS 4
#define MAXFLOW 4 #define MAXFLOW 4