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dmaengine: ipu_idmac: remove redundant irqsave and restore in hardIRQ

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Running in hardIRQ, disabling IRQ is redundant since hardIRQ has disabled
IRQ. This patch removes the irqsave and irqstore to save some instruction
cycles.

Signed-off-by: Barry Song <song.bao.hua@hisilicon.com>
Link: https://lore.kernel.org/r/20201027215252.25820-2-song.bao.hua@hisilicon.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Barry Song
2020-10-28 10:52:43 +13:00
committed by Vinod Koul
parent 69973b4895
commit f3b1024908
1 changed files with 5 additions and 6 deletions
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11
drivers/dma/ipu/ipu_idmac.c
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@@ -1160,14 +1160,13 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
struct idmac_tx_desc *desc, *descnew; struct idmac_tx_desc *desc, *descnew;
bool done = false; bool done = false;
u32 ready0, ready1, curbuf, err; u32 ready0, ready1, curbuf, err;
unsigned long flags;
struct dmaengine_desc_callback cb; struct dmaengine_desc_callback cb;
/* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */ /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer); dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
spin_lock_irqsave(&ipu_data.lock, flags); spin_lock(&ipu_data.lock);
ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY); ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY); ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
@@ -1176,7 +1175,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
if (err & (1 << chan_id)) { if (err & (1 << chan_id)) {
idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4); idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
spin_unlock_irqrestore(&ipu_data.lock, flags); spin_unlock(&ipu_data.lock);
/* /*
* Doing this * Doing this
* ichan->sg[0] = ichan->sg[1] = NULL; * ichan->sg[0] = ichan->sg[1] = NULL;
@@ -1188,7 +1187,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
chan_id, ready0, ready1, curbuf); chan_id, ready0, ready1, curbuf);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
spin_unlock_irqrestore(&ipu_data.lock, flags); spin_unlock(&ipu_data.lock);
/* Other interrupts do not interfere with this channel */ /* Other interrupts do not interfere with this channel */
spin_lock(&ichan->lock); spin_lock(&ichan->lock);
@@ -1251,9 +1250,9 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
if (unlikely(sgnew)) { if (unlikely(sgnew)) {
ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer); ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
} else { } else {
spin_lock_irqsave(&ipu_data.lock, flags); spin_lock(&ipu_data.lock);
ipu_ic_disable_task(&ipu_data, chan_id); ipu_ic_disable_task(&ipu_data, chan_id);
spin_unlock_irqrestore(&ipu_data.lock, flags); spin_unlock(&ipu_data.lock);
ichan->status = IPU_CHANNEL_READY; ichan->status = IPU_CHANNEL_READY;
/* Continue to check for complete descriptor */ /* Continue to check for complete descriptor */
} }