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https://github.com/tbsdtv/linux_media.git
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Merge branch 'clk-unused' into clk-next
- Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver * clk-unused: clk: remove u300 driver clk: remove sirf prima2/atlas drivers clk: remove zte zx driver clk: remove tango4 driver clk: Drop unused efm32gg driver
This commit is contained in:
Stephen Boyd
@@ -1,55 +0,0 @@
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* Clock and reset bindings for CSR atlas7
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Required properties:
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- compatible: Should be "sirf,atlas7-car"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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- #reset-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
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The reset consumer should specify the desired reset by having the reset
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ID in its "reset" phandle cell.
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The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
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Examples: Clock and reset controller node:
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car: clock-controller@18620000 {
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compatible = "sirf,atlas7-car";
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reg = <0x18620000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Examples: Consumers using clock or reset:
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timer@10dc0000 {
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compatible = "sirf,macro-tick";
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reg = <0x10dc0000 0x1000>;
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clocks = <&car 54>;
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interrupts = <0 0 0>,
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<0 1 0>,
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<0 2 0>,
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<0 49 0>,
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<0 50 0>,
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<0 51 0>;
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};
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uart1: uart@18020000 {
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cell-index = <1>;
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compatible = "sirf,macro-uart";
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reg = <0x18020000 0x1000>;
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clocks = <&clks 95>;
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interrupts = <0 18 0>;
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fifosize = <32>;
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};
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vpp@13110000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x13110000 0x10000>;
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interrupts = <0 31 0>;
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clocks = <&car 85>;
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resets = <&car 29>;
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};
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@@ -1,73 +0,0 @@
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* Clock bindings for CSR SiRFprimaII
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Required properties:
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- compatible: Should be "sirf,prima2-clkc"
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- reg: Address and length of the register set
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- interrupts: Should contain clock controller interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of prima2
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clocks and IDs.
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Clock ID
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---------------------------
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rtc 0
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osc 1
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pll1 2
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pll2 3
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pll3 4
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mem 5
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sys 6
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security 7
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dsp 8
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gps 9
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mf 10
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io 11
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cpu 12
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uart0 13
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uart1 14
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uart2 15
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tsc 16
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i2c0 17
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i2c1 18
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spi0 19
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spi1 20
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pwmc 21
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efuse 22
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pulse 23
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dmac0 24
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dmac1 25
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nand 26
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audio 27
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usp0 28
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usp1 29
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usp2 30
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vip 31
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gfx 32
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mm 33
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lcd 34
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vpp 35
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mmc01 36
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mmc23 37
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mmc45 38
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usbpll 39
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usb0 40
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usb1 41
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Examples:
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clks: clock-controller@88000000 {
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compatible = "sirf,prima2-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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i2c0: i2c@b00e0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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clocks = <&clks 17>;
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};
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@@ -1,80 +0,0 @@
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Clock bindings for ST-Ericsson U300 System Controller Clocks
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Bindings for the gated system controller clocks:
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Required properties:
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- compatible: must be "stericsson,u300-syscon-clk"
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- #clock-cells: must be <0>
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- clock-type: specifies the type of clock:
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0 = slow clock
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1 = fast clock
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2 = rest/remaining clock
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- clock-id: specifies the clock in the type range
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Optional properties:
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- clocks: parent clock(s)
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The available clocks per type are as follows:
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Type: ID: Clock:
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-------------------
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0 0 Slow peripheral bridge clock
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0 1 UART0 clock
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0 4 GPIO clock
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0 6 RTC clock
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0 7 Application timer clock
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0 8 Access timer clock
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1 0 Fast peripheral bridge clock
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1 1 I2C bus 0 clock
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1 2 I2C bus 1 clock
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1 5 MMC interface peripheral (silicon) clock
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1 6 SPI clock
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2 3 CPU clock
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2 4 DMA controller clock
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2 5 External Memory Interface (EMIF) clock
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2 6 NAND flask interface clock
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2 8 XGAM graphics engine clock
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2 9 Shared External Memory Interface (SEMI) clock
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2 10 AHB Subsystem Bridge clock
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2 12 Interrupt controller clock
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Example:
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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gpio: gpio@c0016000 {
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compatible = "stericsson,gpio-coh901";
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(...)
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clocks = <&gpio_clk>;
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};
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Bindings for the MMC/SD card clock:
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Required properties:
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- compatible: must be "stericsson,u300-syscon-mclk"
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- #clock-cells: must be <0>
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Optional properties:
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- clocks: parent clock(s)
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mmc_mclk: mmc_mclk {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-mclk";
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clocks = <&mmc_pclk>;
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};
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mmcsd: mmcsd@c0001000 {
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compatible = "arm,pl18x", "arm,primecell";
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clocks = <&mmc_pclk>, <&mmc_mclk>;
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clock-names = "apb_pclk", "mclk";
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(...)
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};
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@@ -1,23 +0,0 @@
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* Sigma Designs Tango4 Clock Generator
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The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
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for RAM and various peripheral devices). The clock binding described here
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is applicable to all Tango4 SoCs.
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Required Properties:
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- compatible: should be "sigma,tango4-clkgen".
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- reg: physical base address of the device and length of memory mapped region.
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- clocks: phandle of the input clock (crystal oscillator).
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- clock-output-names: should be "cpuclk" and "sysclk".
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- #clock-cells: should be set to 1.
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Example:
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clkgen: clkgen@10000 {
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compatible = "sigma,tango4-clkgen";
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reg = <0x10000 0x40>;
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clocks = <&xtal>;
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clock-output-names = "cpuclk", "sysclk";
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#clock-cells = <1>;
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};
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@@ -1,34 +0,0 @@
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Device Tree Clock bindings for ZTE zx296702
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296702-topcrm-clk":
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zx296702 top clock selection, divider and gating
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"zte,zx296702-lsp0crpm-clk" and
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"zte,zx296702-lsp1crpm-clk":
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zx296702 device level clock selection and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
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for the full list of zx296702 clock IDs.
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topclk: topcrm@09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_PCLK>;
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};
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@@ -1,37 +0,0 @@
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Device Tree Clock bindings for ZTE zx296718
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296718-topcrm":
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zx296718 top clock selection, divider and gating
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"zte,zx296718-lsp0crm" and
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"zte,zx296718-lsp1crm":
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zx296718 device level clock selection and gating
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"zte,zx296718-audiocrm":
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zx296718 audio clock selection, divider and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
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for the full list of zx296718 clock IDs.
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topclk: topcrm@1461000 {
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compatible = "zte,zx296718-topcrm-clk";
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reg = <0x01461000 0x1000>;
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#clock-cells = <1>;
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};
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usbphy0:usb-phy0 {
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compatible = "zte,zx296718-usb-phy";
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#phy-cells = <0>;
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clocks = <&topclk USB20_PHY_CLK>;
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clock-names = "phyclk";
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};
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