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dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML format
Add Cadence Sierra PHY bindings in YAML format. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Swapnil Jakhade
committed by
Vinod Koul
Vinod Koul
parent
79caf207d6
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Cadence Sierra PHY
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-----------------------
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Required properties:
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- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
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Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
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- resets: Must contain an entry for each in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include "sierra_reset" and "sierra_apb".
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"sierra_reset" must control the reset line to the PHY.
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"sierra_apb" must control the reset line to the APB PHY
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interface ("sierra_apb" is optional).
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- reg: register range for the PHY.
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- #address-cells: Must be 1
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- #size-cells: Must be 0
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Optional properties:
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- clocks: Must contain an entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must contain "cmn_refclk_dig_div" and
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"cmn_refclk1_dig_div" for configuring the frequency of
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the clock to the lanes. "phy_clk" is deprecated.
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- cdns,autoconf: A boolean property whose presence indicates that the
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PHY registers will be configured by hardware. If not
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present, all sub-node optional properties must be
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provided.
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Sub-nodes:
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Each group of PHY lanes with a single master lane should be represented as
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a sub-node. Note that the actual configuration of each lane is determined by
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hardware strapping, and must match the configuration specified here.
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Sub-node required properties:
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- #phy-cells: Generic PHY binding; must be 0.
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- reg: The master lane number. This is the lowest numbered lane
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in the lane group.
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- resets: Must contain one entry which controls the reset line for the
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master lane of the sub-node.
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See ../reset/reset.txt for details.
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Sub-node optional properties:
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- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
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group is made up of consecutive lanes.
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- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
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configuration of lanes.
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Example:
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pcie_phy4: pcie-phy@fd240000 {
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compatible = "cdns,sierra-phy-t0";
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reg = <0x0 0xfd240000 0x0 0x40000>;
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resets = <&phyrst 0>, <&phyrst 1>;
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reset-names = "sierra_reset", "sierra_apb";
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clocks = <&phyclock>;
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clock-names = "phy_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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pcie0_phy0: pcie-phy@0 {
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reg = <0>;
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resets = <&phyrst 2>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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pcie0_phy1: pcie-phy@2 {
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reg = <2>;
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resets = <&phyrst 4>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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152
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
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152
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence Sierra PHY binding
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description:
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This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
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multiprotocol combinations including protocols such as PCIe, USB etc.
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maintainers:
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- Swapnil Jakhade <sjakhade@cadence.com>
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- Yuti Amonkar <yamonkar@cadence.com>
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properties:
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compatible:
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enum:
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- cdns,sierra-phy-t0
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- ti,sierra-phy-t0
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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resets:
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minItems: 1
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maxItems: 2
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items:
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- description: Sierra PHY reset.
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- description: Sierra APB reset. This is optional.
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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- const: sierra_reset
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- const: sierra_apb
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reg:
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maxItems: 1
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description:
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Offset of the Sierra PHY configuration registers.
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reg-names:
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const: serdes
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: cmn_refclk_dig_div
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- const: cmn_refclk1_dig_div
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cdns,autoconf:
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type: boolean
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description:
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A boolean property whose presence indicates that the PHY registers will be
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configured by hardware. If not present, all sub-node optional properties
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must be provided.
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patternProperties:
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'^phy@[0-9a-f]$':
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type: object
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description:
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Each group of PHY lanes with a single master lane should be represented as
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a sub-node. Note that the actual configuration of each lane is determined
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by hardware strapping, and must match the configuration specified here.
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properties:
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reg:
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description:
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The master lane number. This is the lowest numbered lane in the lane group.
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minimum: 0
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maximum: 15
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resets:
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minItems: 1
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maxItems: 4
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description:
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Contains list of resets, one per lane, to get all the link lanes out of reset.
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"#phy-cells":
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const: 0
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cdns,phy-type:
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description:
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Specifies the type of PHY for which the group of PHY lanes is used.
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Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [2, 4]
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cdns,num-lanes:
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description:
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Number of lanes in this group. The group is made up of consecutive lanes.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 16
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required:
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- reg
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- resets
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- "#phy-cells"
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additionalProperties: false
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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- reg
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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sierra-phy@fd240000 {
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compatible = "cdns,sierra-phy-t0";
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reg = <0x0 0xfd240000 0x0 0x40000>;
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resets = <&phyrst 0>, <&phyrst 1>;
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reset-names = "sierra_reset", "sierra_apb";
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clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
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clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
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#address-cells = <1>;
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#size-cells = <0>;
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pcie0_phy0: phy@0 {
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reg = <0>;
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resets = <&phyrst 2>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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pcie0_phy1: phy@2 {
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reg = <2>;
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resets = <&phyrst 4>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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};
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};
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