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dt-bindings: mtd: marvell-nand: Convert to YAML DT scheme
Switch the DT binding to a YAML schema to enable the DT validation. There was also an incorrect reference to dma-names being "rxtx" where the driver and existing device trees actually use dma-names = "data" so this is corrected in the conversion. Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230619040742.1108172-2-chris.packham@alliedtelesis.co.nz
This commit is contained in:
Vadym Kochan
committed by
Miquel Raynal
Miquel Raynal
parent
bae825ccfd
commit
ad5c18c75d
@@ -0,0 +1,226 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell NAND Flash Controller (NFC)
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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properties:
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compatible:
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oneOf:
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- items:
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- const: marvell,armada-8k-nand-controller
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- const: marvell,armada370-nand-controller
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- enum:
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- marvell,armada370-nand-controller
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- marvell,pxa3xx-nand-controller
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- description: legacy bindings
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deprecated: true
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enum:
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- marvell,armada-8k-nand
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- marvell,armada370-nand
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- marvell,pxa3xx-nand
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description:
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Shall reference the NAND controller clocks, the second one is
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is only needed for the Armada 7K/8K SoCs
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: core
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- const: reg
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: data
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marvell,system-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Syscon node that handles NAND controller related registers
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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$ref: raw-nand-chip.yaml
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properties:
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reg:
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minimum: 0
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maximum: 3
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nand-rb:
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items:
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- minimum: 0
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maximum: 1
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nand-ecc-step-size:
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const: 512
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nand-ecc-strength:
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enum: [1, 4, 8, 12, 16]
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nand-ecc-mode:
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const: hw
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marvell,nand-keep-config:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Orders the driver not to take the timings from the core and
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leaving them completely untouched. Bootloader timings will then
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be used.
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marvell,nand-enable-arbiter:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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To enable the arbiter, all boards blindly used it,
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this bit was set by the bootloader for many boards and even if
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it is marked reserved in several datasheets, it might be needed to set
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it (otherwise it is harmless).
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deprecated: true
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required:
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- reg
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- nand-rb
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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- $ref: nand-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: marvell,pxa3xx-nand-controller
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then:
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required:
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- dmas
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- dma-names
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- if:
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properties:
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compatible:
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contains:
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const: marvell,armada-8k-nand-controller
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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required:
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- marvell,system-controller
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else:
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properties:
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clocks:
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minItems: 1
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clock-names:
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minItems: 1
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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nand_controller: nand-controller@d0000 {
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compatible = "marvell,armada370-nand-controller";
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coredivclk 0>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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marvell,nand-keep-config;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Rootfs";
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reg = <0x00000000 0x40000000>;
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};
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};
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};
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};
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- |
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cp0_nand_controller: nand-controller@720000 {
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&cp0_clk 1 2>,
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<&cp0_clk 1 17>;
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marvell,system-controller = <&cp0_syscon0>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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};
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};
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- |
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nand-controller@43100000 {
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compatible = "marvell,pxa3xx-nand-controller";
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reg = <0x43100000 90>;
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interrupts = <45>;
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clocks = <&clks 1>;
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clock-names = "core";
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dmas = <&pdma 97 3>;
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dma-names = "data";
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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marvell,nand-keep-config;
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};
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};
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...
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@@ -1,126 +0,0 @@
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Marvell NAND Flash Controller (NFC)
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Required properties:
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- compatible: can be one of the following:
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* "marvell,armada-8k-nand-controller"
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* "marvell,armada370-nand-controller"
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* "marvell,pxa3xx-nand-controller"
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* "marvell,armada-8k-nand" (deprecated)
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* "marvell,armada370-nand" (deprecated)
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* "marvell,pxa3xx-nand" (deprecated)
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Compatibles marked deprecated support only the old bindings described
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at the bottom.
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- reg: NAND flash controller memory area.
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- #address-cells: shall be set to 1. Encode the NAND CS.
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- #size-cells: shall be set to 0.
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- interrupts: shall define the NAND controller interrupt.
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- clocks: shall reference the NAND controller clocks, the second one is
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is only needed for the Armada 7K/8K SoCs
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- clock-names: mandatory if there is a second clock, in this case there
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should be one clock named "core" and another one named "reg"
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- marvell,system-controller: Set to retrieve the syscon node that handles
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NAND controller related registers (only required with the
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"marvell,armada-8k-nand[-controller]" compatibles).
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Optional properties:
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- label: see partition.txt. New platforms shall omit this property.
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- dmas: shall reference DMA channel associated to the NAND controller.
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This property is only used with "marvell,pxa3xx-nand[-controller]"
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compatible strings.
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- dma-names: shall be "rxtx".
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This property is only used with "marvell,pxa3xx-nand[-controller]"
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compatible strings.
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Optional children nodes:
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Children nodes represent the available NAND chips.
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Required properties:
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- reg: shall contain the native Chip Select ids (0-3).
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- nand-rb: see nand-controller.yaml (0-1).
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Optional properties:
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- marvell,nand-keep-config: orders the driver not to take the timings
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from the core and leaving them completely untouched. Bootloader
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timings will then be used.
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- label: MTD name.
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- nand-on-flash-bbt: see nand-controller.yaml.
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- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
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- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
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not using hardware ECC. Howerver, it may be added when using hardware
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ECC for clarification but will be ignored by the driver because ECC
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mode is chosen depending on the page size and the strength required by
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the NAND chip. This value may be overwritten with nand-ecc-strength
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property.
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- nand-ecc-strength: see nand-controller.yaml.
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- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
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use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
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step size will shrink or grow in order to fit the required strength.
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Step sizes are not completely random for all and follow certain
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patterns described in AN-379, "Marvell SoC NFC ECC".
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See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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generic bindings.
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Example:
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nand_controller: nand-controller@d0000 {
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compatible = "marvell,armada370-nand-controller";
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coredivclk 0>;
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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marvell,nand-keep-config;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Rootfs";
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reg = <0x00000000 0x40000000>;
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};
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};
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};
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};
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Note on legacy bindings: One can find, in not-updated device trees,
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bindings slightly different than described above with other properties
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described below as well as the partitions node at the root of a so
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called "nand" node (without clear controller/chip separation).
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Legacy properties:
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- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
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used it, this bit was set by the bootloader for many boards and even if
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it is marked reserved in several datasheets, it might be needed to set
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it (otherwise it is harmless) so whether or not this property is set,
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the bit is selected by the driver.
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- num-cs: Number of chip-select lines to use, all boards blindly set 1
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to this and for a reason, other values would have failed. The value of
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this property is ignored.
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Example:
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nand0: nand@43100000 {
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compatible = "marvell,pxa3xx-nand";
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reg = <0x43100000 90>;
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interrupts = <45>;
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dmas = <&pdma 97 0>;
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dma-names = "rxtx";
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#address-cells = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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num-cs = <1>;
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/* Partitions (optional) */
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};
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@@ -12525,7 +12525,6 @@ MARVELL NAND CONTROLLER DRIVER
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M: Miquel Raynal <miquel.raynal@bootlin.com>
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M: Miquel Raynal <miquel.raynal@bootlin.com>
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L: linux-mtd@lists.infradead.org
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L: linux-mtd@lists.infradead.org
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S: Maintained
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S: Maintained
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F: Documentation/devicetree/bindings/mtd/marvell-nand.txt
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F: drivers/mtd/nand/raw/marvell_nand.c
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F: drivers/mtd/nand/raw/marvell_nand.c
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MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
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MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
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Reference in New Issue
Block a user