mirror of
https://github.com/tbsdtv/linux_media.git
synced 2025-07-23 12:43:29 +02:00
Merge branches 'clk-qcom' and 'clk-microchip' into clk-next
* clk-qcom: (63 commits) clk: qcom: gcc-sc8280xp: Add runtime PM clk: qcom: gpucc-sc8280xp: Add runtime PM clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags clk: qcom: gpucc-sm6375: Enable runtime pm dt-bindings: clock: sm6375-gpucc: Add VDD_GX clk: qcom: gcc-sm6115: Add missing PLL config properties clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) clk: qcom: gcc-ipq6018: remove duplicate initializers clk: qcom: gcc-ipq9574: Enable crypto clocks dt-bindings: clock: Add crypto clock and reset definitions clk: qcom: Add lpass audio clock controller driver for SC8280XP clk: qcom: Add lpass clock controller driver for SC8280XP dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 clk: qcom: gpucc-sm8550: Add support for graphics clock controller clk: qcom: Add support for SM8450 GPUCC clk: qcom: gcc-sm8450: Enable hw_clk_ctrl clk: qcom: rcg2: Make hw_clk_ctrl toggleable dt-bindings: clock: qcom: Add SM8550 graphics clock controller ... * clk-microchip: clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id clk: at91: sama7g5: switch to parent_hw and parent_data clk: at91: sckc: switch to parent_data/parent_hw clk: at91: clk-sam9x60-pll: add support for parent_hw clk: at91: clk-utmi: add support for parent_hw clk: at91: clk-system: add support for parent_hw clk: at91: clk-programmable: add support for parent_hw clk: at91: clk-peripheral: add support for parent_hw clk: at91: clk-master: add support for parent_hw clk: at91: clk-generated: add support for parent_hw clk: at91: clk-main: add support for parent_data/parent_hw
This commit is contained in:
Stephen Boyd
@@ -210,4 +210,8 @@
|
||||
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
|
||||
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
|
||||
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
|
||||
#define GCC_CRYPTO_CLK_SRC 204
|
||||
#define GCC_CRYPTO_CLK 205
|
||||
#define GCC_CRYPTO_AXI_CLK 206
|
||||
#define GCC_CRYPTO_AHB_CLK 207
|
||||
#endif
|
||||
|
||||
17
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
Normal file
17
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
|
||||
|
||||
/* LPASS AUDIO CC CSR */
|
||||
#define LPASS_AUDIO_SWR_RX_CGCR 0
|
||||
#define LPASS_AUDIO_SWR_WSA_CGCR 1
|
||||
#define LPASS_AUDIO_SWR_WSA2_CGCR 2
|
||||
|
||||
/* LPASS TCSR */
|
||||
#define LPASS_AUDIO_SWR_TX_CGCR 0
|
||||
|
||||
#endif
|
||||
193
include/dt-bindings/clock/qcom,sdx75-gcc.h
Normal file
193
include/dt-bindings/clock/qcom,sdx75-gcc.h
Normal file
@@ -0,0 +1,193 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GPLL0 0
|
||||
#define GPLL0_OUT_EVEN 1
|
||||
#define GPLL4 2
|
||||
#define GPLL5 3
|
||||
#define GPLL6 4
|
||||
#define GPLL8 5
|
||||
#define GCC_AHB_PCIE_LINK_CLK 6
|
||||
#define GCC_BOOT_ROM_AHB_CLK 7
|
||||
#define GCC_EEE_EMAC0_CLK 8
|
||||
#define GCC_EEE_EMAC0_CLK_SRC 9
|
||||
#define GCC_EEE_EMAC1_CLK 10
|
||||
#define GCC_EEE_EMAC1_CLK_SRC 11
|
||||
#define GCC_EMAC0_AXI_CLK 12
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15
|
||||
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16
|
||||
#define GCC_EMAC0_PHY_AUX_CLK 17
|
||||
#define GCC_EMAC0_PHY_AUX_CLK_SRC 18
|
||||
#define GCC_EMAC0_PTP_CLK 19
|
||||
#define GCC_EMAC0_PTP_CLK_SRC 20
|
||||
#define GCC_EMAC0_RGMII_CLK 21
|
||||
#define GCC_EMAC0_RGMII_CLK_SRC 22
|
||||
#define GCC_EMAC0_RPCS_RX_CLK 23
|
||||
#define GCC_EMAC0_RPCS_TX_CLK 24
|
||||
#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25
|
||||
#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26
|
||||
#define GCC_EMAC0_SLV_AHB_CLK 27
|
||||
#define GCC_EMAC0_XGXS_RX_CLK 28
|
||||
#define GCC_EMAC0_XGXS_TX_CLK 29
|
||||
#define GCC_EMAC1_AXI_CLK 30
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33
|
||||
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34
|
||||
#define GCC_EMAC1_PHY_AUX_CLK 35
|
||||
#define GCC_EMAC1_PHY_AUX_CLK_SRC 36
|
||||
#define GCC_EMAC1_PTP_CLK 37
|
||||
#define GCC_EMAC1_PTP_CLK_SRC 38
|
||||
#define GCC_EMAC1_RGMII_CLK 39
|
||||
#define GCC_EMAC1_RGMII_CLK_SRC 40
|
||||
#define GCC_EMAC1_RPCS_RX_CLK 41
|
||||
#define GCC_EMAC1_RPCS_TX_CLK 42
|
||||
#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43
|
||||
#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44
|
||||
#define GCC_EMAC1_SLV_AHB_CLK 45
|
||||
#define GCC_EMAC1_XGXS_RX_CLK 46
|
||||
#define GCC_EMAC1_XGXS_TX_CLK 47
|
||||
#define GCC_EMAC_0_CLKREF_EN 48
|
||||
#define GCC_EMAC_1_CLKREF_EN 49
|
||||
#define GCC_GP1_CLK 50
|
||||
#define GCC_GP1_CLK_SRC 51
|
||||
#define GCC_GP2_CLK 52
|
||||
#define GCC_GP2_CLK_SRC 53
|
||||
#define GCC_GP3_CLK 54
|
||||
#define GCC_GP3_CLK_SRC 55
|
||||
#define GCC_PCIE_0_CLKREF_EN 56
|
||||
#define GCC_PCIE_1_AUX_CLK 57
|
||||
#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 59
|
||||
#define GCC_PCIE_1_CLKREF_EN 60
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 61
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK 62
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63
|
||||
#define GCC_PCIE_1_PIPE_CLK 64
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 65
|
||||
#define GCC_PCIE_1_PIPE_DIV2_CLK 66
|
||||
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 68
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69
|
||||
#define GCC_PCIE_2_AUX_CLK 70
|
||||
#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71
|
||||
#define GCC_PCIE_2_CFG_AHB_CLK 72
|
||||
#define GCC_PCIE_2_CLKREF_EN 73
|
||||
#define GCC_PCIE_2_MSTR_AXI_CLK 74
|
||||
#define GCC_PCIE_2_PHY_RCHNG_CLK 75
|
||||
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76
|
||||
#define GCC_PCIE_2_PIPE_CLK 77
|
||||
#define GCC_PCIE_2_PIPE_CLK_SRC 78
|
||||
#define GCC_PCIE_2_PIPE_DIV2_CLK 79
|
||||
#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80
|
||||
#define GCC_PCIE_2_SLV_AXI_CLK 81
|
||||
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82
|
||||
#define GCC_PCIE_AUX_CLK 83
|
||||
#define GCC_PCIE_AUX_CLK_SRC 84
|
||||
#define GCC_PCIE_AUX_PHY_CLK_SRC 85
|
||||
#define GCC_PCIE_CFG_AHB_CLK 86
|
||||
#define GCC_PCIE_MSTR_AXI_CLK 87
|
||||
#define GCC_PCIE_PIPE_CLK 88
|
||||
#define GCC_PCIE_PIPE_CLK_SRC 89
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK 90
|
||||
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91
|
||||
#define GCC_PCIE_SLEEP_CLK 92
|
||||
#define GCC_PCIE_SLV_AXI_CLK 93
|
||||
#define GCC_PCIE_SLV_Q2A_AXI_CLK 94
|
||||
#define GCC_PDM2_CLK 95
|
||||
#define GCC_PDM2_CLK_SRC 96
|
||||
#define GCC_PDM_AHB_CLK 97
|
||||
#define GCC_PDM_XO4_CLK 98
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 100
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 101
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 103
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 105
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 107
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 109
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 111
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 113
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 115
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116
|
||||
#define GCC_QUPV3_WRAP0_S8_CLK 117
|
||||
#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120
|
||||
#define GCC_SDCC1_AHB_CLK 121
|
||||
#define GCC_SDCC1_APPS_CLK 122
|
||||
#define GCC_SDCC1_APPS_CLK_SRC 123
|
||||
#define GCC_SDCC2_AHB_CLK 124
|
||||
#define GCC_SDCC2_APPS_CLK 125
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 126
|
||||
#define GCC_USB2_CLKREF_EN 127
|
||||
#define GCC_USB30_MASTER_CLK 128
|
||||
#define GCC_USB30_MASTER_CLK_SRC 129
|
||||
#define GCC_USB30_MOCK_UTMI_CLK 130
|
||||
#define GCC_USB30_MOCK_UTMI_CLK_SRC 131
|
||||
#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132
|
||||
#define GCC_USB30_MSTR_AXI_CLK 133
|
||||
#define GCC_USB30_SLEEP_CLK 134
|
||||
#define GCC_USB30_SLV_AHB_CLK 135
|
||||
#define GCC_USB3_PHY_AUX_CLK 136
|
||||
#define GCC_USB3_PHY_AUX_CLK_SRC 137
|
||||
#define GCC_USB3_PHY_PIPE_CLK 138
|
||||
#define GCC_USB3_PHY_PIPE_CLK_SRC 139
|
||||
#define GCC_USB3_PRIM_CLKREF_EN 140
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141
|
||||
#define GCC_XO_PCIE_LINK_CLK 142
|
||||
|
||||
/* GCC power domains */
|
||||
#define GCC_EMAC0_GDSC 0
|
||||
#define GCC_EMAC1_GDSC 1
|
||||
#define GCC_PCIE_1_GDSC 2
|
||||
#define GCC_PCIE_1_PHY_GDSC 3
|
||||
#define GCC_PCIE_2_GDSC 4
|
||||
#define GCC_PCIE_2_PHY_GDSC 5
|
||||
#define GCC_PCIE_GDSC 6
|
||||
#define GCC_PCIE_PHY_GDSC 7
|
||||
#define GCC_USB30_GDSC 8
|
||||
#define GCC_USB3_PHY_GDSC 9
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_EMAC0_BCR 0
|
||||
#define GCC_EMAC1_BCR 1
|
||||
#define GCC_EMMC_BCR 2
|
||||
#define GCC_PCIE_1_BCR 3
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 4
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5
|
||||
#define GCC_PCIE_1_PHY_BCR 6
|
||||
#define GCC_PCIE_2_BCR 7
|
||||
#define GCC_PCIE_2_LINK_DOWN_BCR 8
|
||||
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9
|
||||
#define GCC_PCIE_2_PHY_BCR 10
|
||||
#define GCC_PCIE_BCR 11
|
||||
#define GCC_PCIE_LINK_DOWN_BCR 12
|
||||
#define GCC_PCIE_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_BCR 14
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
|
||||
#define GCC_PCIE_PHY_COM_BCR 16
|
||||
#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17
|
||||
#define GCC_QUSB2PHY_BCR 18
|
||||
#define GCC_TCSR_PCIE_BCR 19
|
||||
#define GCC_USB30_BCR 20
|
||||
#define GCC_USB3_PHY_BCR 21
|
||||
#define GCC_USB3PHY_PHY_BCR 22
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
|
||||
#define GCC_EMAC0_RGMII_CLK_ARES 24
|
||||
|
||||
#endif
|
||||
35
include/dt-bindings/clock/qcom,sm8350-videocc.h
Normal file
35
include/dt-bindings/clock/qcom,sm8350-videocc.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
|
||||
|
||||
/* Clocks */
|
||||
#define VIDEO_CC_AHB_CLK_SRC 0
|
||||
#define VIDEO_CC_MVS0_CLK 1
|
||||
#define VIDEO_CC_MVS0_CLK_SRC 2
|
||||
#define VIDEO_CC_MVS0_DIV_CLK_SRC 3
|
||||
#define VIDEO_CC_MVS0C_CLK 4
|
||||
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5
|
||||
#define VIDEO_CC_MVS1_CLK 6
|
||||
#define VIDEO_CC_MVS1_CLK_SRC 7
|
||||
#define VIDEO_CC_MVS1_DIV2_CLK 8
|
||||
#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
|
||||
#define VIDEO_CC_MVS1C_CLK 10
|
||||
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
|
||||
#define VIDEO_CC_SLEEP_CLK 12
|
||||
#define VIDEO_CC_SLEEP_CLK_SRC 13
|
||||
#define VIDEO_CC_XO_CLK_SRC 14
|
||||
#define VIDEO_PLL0 15
|
||||
#define VIDEO_PLL1 16
|
||||
|
||||
/* GDSCs */
|
||||
#define MVS0C_GDSC 0
|
||||
#define MVS1C_GDSC 1
|
||||
#define MVS0_GDSC 2
|
||||
#define MVS1_GDSC 3
|
||||
|
||||
#endif
|
||||
48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
Normal file
48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
|
||||
|
||||
/* Clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CRC_AHB_CLK 1
|
||||
#define GPU_CC_CX_APB_CLK 2
|
||||
#define GPU_CC_CX_FF_CLK 3
|
||||
#define GPU_CC_CX_GMU_CLK 4
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 5
|
||||
#define GPU_CC_CXO_AON_CLK 6
|
||||
#define GPU_CC_CXO_CLK 7
|
||||
#define GPU_CC_DEMET_CLK 8
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 9
|
||||
#define GPU_CC_FF_CLK_SRC 10
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 11
|
||||
#define GPU_CC_GMU_CLK_SRC 12
|
||||
#define GPU_CC_GX_FF_CLK 13
|
||||
#define GPU_CC_GX_GFX3D_CLK 14
|
||||
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
|
||||
#define GPU_CC_GX_GMU_CLK 16
|
||||
#define GPU_CC_GX_VSENSE_CLK 17
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
|
||||
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19
|
||||
#define GPU_CC_HUB_AON_CLK 20
|
||||
#define GPU_CC_HUB_CLK_SRC 21
|
||||
#define GPU_CC_HUB_CX_INT_CLK 22
|
||||
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 24
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 25
|
||||
#define GPU_CC_MND1X_1_GFX3D_CLK 26
|
||||
#define GPU_CC_PLL0 27
|
||||
#define GPU_CC_PLL1 28
|
||||
#define GPU_CC_SLEEP_CLK 29
|
||||
#define GPU_CC_XO_CLK_SRC 30
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 31
|
||||
|
||||
/* GDSCs */
|
||||
#define GPU_GX_GDSC 0
|
||||
#define GPU_CX_GDSC 1
|
||||
|
||||
#endif
|
||||
38
include/dt-bindings/clock/qcom,sm8450-videocc.h
Normal file
38
include/dt-bindings/clock/qcom,sm8450-videocc.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
|
||||
|
||||
/* VIDEO_CC clocks */
|
||||
#define VIDEO_CC_MVS0_CLK 0
|
||||
#define VIDEO_CC_MVS0_CLK_SRC 1
|
||||
#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
|
||||
#define VIDEO_CC_MVS0C_CLK 3
|
||||
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
|
||||
#define VIDEO_CC_MVS1_CLK 5
|
||||
#define VIDEO_CC_MVS1_CLK_SRC 6
|
||||
#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
|
||||
#define VIDEO_CC_MVS1C_CLK 8
|
||||
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
|
||||
#define VIDEO_CC_PLL0 10
|
||||
#define VIDEO_CC_PLL1 11
|
||||
|
||||
/* VIDEO_CC power domains */
|
||||
#define VIDEO_CC_MVS0C_GDSC 0
|
||||
#define VIDEO_CC_MVS0_GDSC 1
|
||||
#define VIDEO_CC_MVS1C_GDSC 2
|
||||
#define VIDEO_CC_MVS1_GDSC 3
|
||||
|
||||
/* VIDEO_CC resets */
|
||||
#define CVP_VIDEO_CC_INTERFACE_BCR 0
|
||||
#define CVP_VIDEO_CC_MVS0_BCR 1
|
||||
#define CVP_VIDEO_CC_MVS0C_BCR 2
|
||||
#define CVP_VIDEO_CC_MVS1_BCR 3
|
||||
#define CVP_VIDEO_CC_MVS1C_BCR 4
|
||||
#define VIDEO_CC_MVS0C_CLK_ARES 5
|
||||
#define VIDEO_CC_MVS1C_CLK_ARES 6
|
||||
|
||||
#endif
|
||||
48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
Normal file
48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
|
||||
|
||||
/* GPU_CC clocks */
|
||||
#define GPU_CC_AHB_CLK 0
|
||||
#define GPU_CC_CRC_AHB_CLK 1
|
||||
#define GPU_CC_CX_FF_CLK 2
|
||||
#define GPU_CC_CX_GMU_CLK 3
|
||||
#define GPU_CC_CXO_AON_CLK 4
|
||||
#define GPU_CC_CXO_CLK 5
|
||||
#define GPU_CC_DEMET_CLK 6
|
||||
#define GPU_CC_DEMET_DIV_CLK_SRC 7
|
||||
#define GPU_CC_FF_CLK_SRC 8
|
||||
#define GPU_CC_FREQ_MEASURE_CLK 9
|
||||
#define GPU_CC_GMU_CLK_SRC 10
|
||||
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
|
||||
#define GPU_CC_HUB_AON_CLK 12
|
||||
#define GPU_CC_HUB_CLK_SRC 13
|
||||
#define GPU_CC_HUB_CX_INT_CLK 14
|
||||
#define GPU_CC_MEMNOC_GFX_CLK 15
|
||||
#define GPU_CC_MND1X_0_GFX3D_CLK 16
|
||||
#define GPU_CC_MND1X_1_GFX3D_CLK 17
|
||||
#define GPU_CC_PLL0 18
|
||||
#define GPU_CC_PLL1 19
|
||||
#define GPU_CC_SLEEP_CLK 20
|
||||
#define GPU_CC_XO_CLK_SRC 21
|
||||
#define GPU_CC_XO_DIV_CLK_SRC 22
|
||||
|
||||
/* GPU_CC power domains */
|
||||
#define GPU_CC_CX_GDSC 0
|
||||
#define GPU_CC_GX_GDSC 1
|
||||
|
||||
/* GPU_CC resets */
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CX_BCR 1
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
|
||||
#define GPUCC_GPU_CC_FF_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
|
||||
#endif
|
||||
@@ -160,5 +160,6 @@
|
||||
#define GCC_WCSS_Q6_BCR 151
|
||||
#define GCC_WCSS_Q6_TBU_BCR 152
|
||||
#define GCC_TCSR_BCR 153
|
||||
#define GCC_CRYPTO_BCR 154
|
||||
|
||||
#endif
|
||||
|
||||
18
include/dt-bindings/reset/qcom,sm8350-videocc.h
Normal file
18
include/dt-bindings/reset/qcom,sm8350-videocc.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
|
||||
#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H
|
||||
|
||||
#define VIDEO_CC_CVP_INTERFACE_BCR 0
|
||||
#define VIDEO_CC_CVP_MVS0_BCR 1
|
||||
#define VIDEO_CC_MVS0C_CLK_ARES 2
|
||||
#define VIDEO_CC_CVP_MVS0C_BCR 3
|
||||
#define VIDEO_CC_CVP_MVS1_BCR 4
|
||||
#define VIDEO_CC_MVS1C_CLK_ARES 5
|
||||
#define VIDEO_CC_CVP_MVS1C_BCR 6
|
||||
|
||||
#endif
|
||||
20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
Normal file
20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
|
||||
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
|
||||
|
||||
#define GPUCC_GPU_CC_ACD_BCR 0
|
||||
#define GPUCC_GPU_CC_CX_BCR 1
|
||||
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
|
||||
#define GPUCC_GPU_CC_FF_BCR 3
|
||||
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
|
||||
#define GPUCC_GPU_CC_GMU_BCR 5
|
||||
#define GPUCC_GPU_CC_GX_BCR 6
|
||||
#define GPUCC_GPU_CC_XO_BCR 7
|
||||
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user