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PCI: Replace http:// links with https://

Browse Source 
Replace http:// links with https:// links.  This reduces the likelihood of
man-in-the-middle attacks when developers open these links.

  Deterministic algorithm:
  For each file:
    If not .svg:
      For each line:
	If doesn't contain `\bxmlns\b`:
	  For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	    If both the HTTP and HTTPS versions
	    return 200 OK and serve the same content:
	      Replace HTTP with HTTPS.

[bhelgaas: also update samsung.com links, drop sourceforge link]
Link: https://lore.kernel.org/r/20200627103050.71712-1-grandmaster@al2klimov.de
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Alexander A. Klimov
2020-06-27 12:30:50 +02:00
committed by Bjorn Helgaas
parent b91535812d
commit 7ecd4a8175
15 changed files with 23 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/PCI/pci.rst
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@@ -17,7 +17,7 @@ PCI device drivers.
A more complete resource is the third edition of "Linux Device Drivers" A more complete resource is the third edition of "Linux Device Drivers"
by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman. by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
LDD3 is available for free (under Creative Commons License) from: LDD3 is available for free (under Creative Commons License) from:
http://lwn.net/Kernel/LDD3/. https://lwn.net/Kernel/LDD3/.
However, keep in mind that all documents are subject to "bit rot". However, keep in mind that all documents are subject to "bit rot".
Refer to the source code if things are not working as described here. Refer to the source code if things are not working as described here.
@@ -514,9 +514,8 @@ your driver if they're helpful, or just use plain hex constants.
The device IDs are arbitrary hex numbers (vendor controlled) and normally used The device IDs are arbitrary hex numbers (vendor controlled) and normally used
only in a single location, the pci_device_id table. only in a single location, the pci_device_id table.
Please DO submit new vendor/device IDs to http://pci-ids.ucw.cz/. Please DO submit new vendor/device IDs to https://pci-ids.ucw.cz/.
There are mirrors of the pci.ids file at http://pciids.sourceforge.net/ There's a mirror of the pci.ids file at https://github.com/pciutils/pciids.
and https://github.com/pciutils/pciids.
Obsolete functions Obsolete functions

4
Documentation/devicetree/bindings/pci/pci.txt
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@@ -1,12 +1,12 @@
PCI bus bridges have standardized Device Tree bindings: PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994 PCI Bus Binding to: IEEE Std 1275-1994
http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part: And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping Open Firmware Recommended Practice: Interrupt Mapping
http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties: driver implementation may support the following properties:

4
arch/x86/pci/fixup.c
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@@ -557,12 +557,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_z
* Device [8086:2fc0] * Device [8086:2fc0]
* Erratum HSE43 * Erratum HSE43
* CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
* *
* Devices [8086:6f60,6fa0,6fc0] * Devices [8086:6f60,6fa0,6fc0]
* Erratum BDF2 * Erratum BDF2
* PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
*/ */
static void pci_invalid_bar(struct pci_dev *dev) static void pci_invalid_bar(struct pci_dev *dev)
{ {

2
drivers/pci/controller/dwc/pci-dra7xx.c
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@@ -2,7 +2,7 @@
/* /*
* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
* *
* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
* *
* Authors: Kishon Vijay Abraham I <kishon@ti.com> * Authors: Kishon Vijay Abraham I <kishon@ti.com>
*/ */

2
drivers/pci/controller/dwc/pci-exynos.c
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@@ -3,7 +3,7 @@
* PCIe host controller driver for Samsung Exynos SoCs * PCIe host controller driver for Samsung Exynos SoCs
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pci-imx6.c
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@@ -3,7 +3,7 @@
* PCIe host controller driver for Freescale i.MX6 SoCs * PCIe host controller driver for Freescale i.MX6 SoCs
* *
* Copyright (C) 2013 Kosagi * Copyright (C) 2013 Kosagi
* http://www.kosagi.com * https://www.kosagi.com
* *
* Author: Sean Cross <xobs@kosagi.com> * Author: Sean Cross <xobs@kosagi.com>
*/ */

2
drivers/pci/controller/dwc/pci-keystone.c
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@@ -3,7 +3,7 @@
* PCIe host controller driver for Texas Instruments Keystone SoCs * PCIe host controller driver for Texas Instruments Keystone SoCs
* *
* Copyright (C) 2013-2014 Texas Instruments., Ltd. * Copyright (C) 2013-2014 Texas Instruments., Ltd.
* http://www.ti.com * https://www.ti.com
* *
* Author: Murali Karicheri <m-karicheri2@ti.com> * Author: Murali Karicheri <m-karicheri2@ti.com>
* Implementation based on pci-exynos.c and pcie-designware.c * Implementation based on pci-exynos.c and pcie-designware.c

2
drivers/pci/controller/dwc/pcie-designware-host.c
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@@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-designware.c
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@@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-designware.h
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@@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-kirin.c
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@@ -3,7 +3,7 @@
* PCIe host controller driver for Kirin Phone SoCs * PCIe host controller driver for Kirin Phone SoCs
* *
* Copyright (C) 2017 HiSilicon Electronics Co., Ltd. * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
* http://www.huawei.com * https://www.huawei.com
* *
* Author: Xiaowei Song <songxiaowei@huawei.com> * Author: Xiaowei Song <songxiaowei@huawei.com>
*/ */

2
drivers/pci/pci-label.c
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@@ -18,7 +18,7 @@
* the instance number and string from the type 41 record and exports * the instance number and string from the type 41 record and exports
* it to sysfs. * it to sysfs.
* *
* Please see http://linux.dell.com/files/biosdevname/ for more * Please see https://linux.dell.com/files/biosdevname/ for more
* information. * information.
*/ */

2
drivers/pci/pcie/Kconfig
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@@ -43,7 +43,7 @@ config PCIEAER_INJECT
error injection can fake almost all kinds of errors with the error injection can fake almost all kinds of errors with the
help of a user space helper tool aer-inject, which can be help of a user space helper tool aer-inject, which can be
gotten from: gotten from:
http://www.kernel.org/pub/linux/utils/pci/aer-inject/ https://www.kernel.org/pub/linux/utils/pci/aer-inject/
# #
# PCI Express ECRC # PCI Express ECRC

2
drivers/pci/pcie/aer_inject.c
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@@ -6,7 +6,7 @@
* trigger various real hardware errors. Software based error * trigger various real hardware errors. Software based error
* injection can fake almost all kinds of errors with the help of a * injection can fake almost all kinds of errors with the help of a
* user space helper tool aer-inject, which can be gotten from: * user space helper tool aer-inject, which can be gotten from:
* http://www.kernel.org/pub/linux/utils/pci/aer-inject/ * https://www.kernel.org/pub/linux/utils/pci/aer-inject/
* *
* Copyright 2009 Intel Corporation. * Copyright 2009 Intel Corporation.
* Huang Ying <ying.huang@intel.com> * Huang Ying <ying.huang@intel.com>

10
drivers/pci/quirks.c
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@@ -4620,11 +4620,11 @@ static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
* *
* 0x9d10-0x9d1b PCI Express Root port #{1-12} * 0x9d10-0x9d1b PCI Express Root port #{1-12}
* *
* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
* [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
* [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
* [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
* [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
*/ */