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doc: Rewrite confusing statement about memory barriers

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The "Write (or store) memory barriers" bullet of the "Variety of memory
barriers" section, calls out a sequential order of stores, which is
confusing since sequential ordering is not guaranteed.

This commit therefore rewords to avoid mentioning a sequence of stores
to clarify the intent.

Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
This commit is contained in:
Guilherme G. Piccoli
2017-09-21 16:29:01 -03:00
committed by Paul E. McKenney
parent d92f842bb3
commit 5692fcc671
1 changed files with 2 additions and 2 deletions
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4
Documentation/memory-barriers.txt
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@@ -383,8 +383,8 @@ Memory barriers come in four basic varieties:
to have any effect on loads. to have any effect on loads.
A CPU can be viewed as committing a sequence of store operations to the A CPU can be viewed as committing a sequence of store operations to the
memory system as time progresses. All stores before a write barrier will memory system as time progresses. All stores _before_ a write barrier
occur in the sequence _before_ all the stores after the write barrier. will occur _before_ all the stores after the write barrier.
[!] Note that write barriers should normally be paired with read or data [!] Note that write barriers should normally be paired with read or data
dependency barriers; see the "SMP barrier pairing" subsection. dependency barriers; see the "SMP barrier pairing" subsection.