mirror of
https://github.com/tbsdtv/linux_media.git
synced 2025-07-23 12:43:29 +02:00
Merge tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:
phy-for-5.12
- Updates:
- Conversion to YAML binding for:
- mtk-xsphy
- mtk-tphy
- mtk-ufs
- HDMI PHY
- MIPI DSI PHY
- brcmstb-usb-phy
- Support for BCM4908 usb phy
- Support for Qualcomm SDX55 USB and QMP phy
- Support for Qualcomm SM8350 aka Snapdragon 888 UFS and USB phy
- Support for Qualcomm SDM660 USB and UFS phy
- Support for Qualcomm SC8180X USB and UFS phy
- Support for Qualcomm IPQ6018 USB phy
- Stm32 phy updates
* tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
phy: cpcap-usb: Simplify bool conversion
phy: qcom-qmp: make a const array static, makes object smaller
phy: zynqmp: Simplify code by using dev_err_probe()
phy: qcom-qmp: Add support for SM8350 UFS phy
phy: qcom-qmp: Add UFS V5 registers found in SM8350
dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
phy: qualcomm: usb28nm: Add MDM9607 init sequence
dt-bindings: phy: qcom,qusb2: document ipq6018 compatible
phy: qcom-qusb2: add QUSB2 support for IPQ6018
phy: qcom-qmp: Add SC8180X USB phy
phy: qcom-qmp: Add SC8180X UFS phy
dt-bindings: phy: qcom,qmp: Add SC8180X USB phy
dt-bindings: phy: qcom,qmp: Add SC8180X UFS to the QMP binding
dt-bindings: phy: qcom-qusb2: Document SDM660 compatible
phy: qcom-qusb2: Add configuration for SDM660
phy: qcom-qusb2: Allow specifying default clock scheme
dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350 bindings
phy: qcom-qmp: Add SM8350 USB QMP PHYs
dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY bindings
phy: qcom-qmp: Add support for SDX55 QMP PHY
...
This commit is contained in:
Greg Kroah-Hartman
@@ -22,23 +22,7 @@ Required properties:
|
|||||||
MIPI TX Configuration Module
|
MIPI TX Configuration Module
|
||||||
============================
|
============================
|
||||||
|
|
||||||
The MIPI TX configuration module controls the MIPI D-PHY.
|
See phy/mediatek,dsi-phy.yaml
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: "mediatek,<chip>-mipi-tx"
|
|
||||||
- the supported chips are mt2701, 7623, mt8173 and mt8183.
|
|
||||||
- reg: Physical base address and length of the controller's registers
|
|
||||||
- clocks: PLL reference clock
|
|
||||||
- clock-output-names: name of the output clock line to the DSI encoder
|
|
||||||
- #clock-cells: must be <0>;
|
|
||||||
- #phy-cells: must be <0>.
|
|
||||||
|
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Optional properties:
|
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||||||
- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
|
|
||||||
the step is 200.
|
|
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- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
|
|
||||||
unspecified default values shall be used.
|
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||||||
- nvmem-cell-names: Should be "calibration-data"
|
|
||||||
|
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Example:
|
Example:
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|
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|
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@@ -53,23 +53,7 @@ Required properties:
|
|||||||
|
|
||||||
HDMI PHY
|
HDMI PHY
|
||||||
========
|
========
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|
See phy/mediatek,hdmi-phy.yaml
|
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The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
|
|
||||||
output and drives the HDMI pads.
|
|
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|
|
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Required properties:
|
|
||||||
- compatible: "mediatek,<chip>-hdmi-phy"
|
|
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- the supported chips are mt2701, mt7623 and mt8173
|
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- reg: Physical base address and length of the module's registers
|
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- clocks: PLL reference clock
|
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- clock-names: must contain "pll_ref"
|
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- clock-output-names: must be "hdmitx_dig_cts" on mt8173
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- #phy-cells: must be <0>
|
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- #clock-cells: must be <0>
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Optional properties:
|
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- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
|
|
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- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
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|
||||||
|
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Example:
|
Example:
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|
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@@ -1,86 +0,0 @@
|
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Broadcom STB USB PHY
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|
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Required properties:
|
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- compatible: should be one of
|
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"brcm,brcmstb-usb-phy"
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"brcm,bcm7216-usb-phy"
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"brcm,bcm7211-usb-phy"
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|
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|
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- reg and reg-names properties requirements are specific to the
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|
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compatible string.
|
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"brcm,brcmstb-usb-phy":
|
|
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- reg: 1 or 2 offset and length pairs. One for the base CTRL registers
|
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and an optional pair for systems with USB 3.x support
|
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- reg-names: not specified
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"brcm,bcm7216-usb-phy":
|
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- reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL
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registers
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- reg-names: "ctrl", "xhci_ec", "xhci_gbl"
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"brcm,bcm7211-usb-phy":
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- reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL,
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USB_PHY and USB_MDIO registers and an optional pair
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for the BDC registers
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- reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec"
|
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|
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- #phy-cells: Shall be 1 as it expects one argument for setting
|
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the type of the PHY. Possible values are:
|
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- PHY_TYPE_USB2 for USB1.1/2.0 PHY
|
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- PHY_TYPE_USB3 for USB3.x PHY
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Optional Properties:
|
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- clocks : clock phandles.
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- clock-names: String, clock name.
|
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- interrupts: wakeup interrupt
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- interrupt-names: "wakeup"
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- brcm,ipp: Boolean, Invert Port Power.
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Possible values are: 0 (Don't invert), 1 (Invert)
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- brcm,ioc: Boolean, Invert Over Current detection.
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Possible values are: 0 (Don't invert), 1 (Invert)
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- dr_mode: String, PHY Device mode.
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Possible values are: "host", "peripheral ", "drd" or "typec-pd"
|
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If this property is not defined, the phy will default to "host" mode.
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- brcm,syscon-piarbctl: phandle to syscon for handling config registers
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NOTE: one or both of the following two properties must be set
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- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
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- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
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|
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Example:
|
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|
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usbphy_0: usb-phy@f0470200 {
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reg = <0xf0470200 0xb8>,
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<0xf0471940 0x6c0>;
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compatible = "brcm,brcmstb-usb-phy";
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#phy-cells = <1>;
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dr_mode = "host"
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brcm,ioc = <1>;
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brcm,ipp = <1>;
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brcm,has-xhci;
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brcm,has-eohci;
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clocks = <&usb20>, <&usb30>;
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clock-names = "sw_usb", "sw_usb3";
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};
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usb-phy@29f0200 {
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reg = <0x29f0200 0x200>,
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<0x29c0880 0x30>,
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<0x29cc100 0x534>,
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<0x2808000 0x24>,
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<0x2980080 0x8>;
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reg-names = "ctrl",
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"xhci_ec",
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"xhci_gbl",
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"usb_phy",
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"usb_mdio";
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brcm,ioc = <0x0>;
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brcm,ipp = <0x0>;
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compatible = "brcm,bcm7211-usb-phy";
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interrupts = <0x30>;
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interrupt-parent = <&vpu_intr1_nosec_intc>;
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interrupt-names = "wake";
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#phy-cells = <0x1>;
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brcm,has-xhci;
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syscon-piarbctl = <&syscon_piarbctl>;
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clocks = <&scmi_clk 256>;
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clock-names = "sw_usb";
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};
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196
Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
Normal file
196
Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
Normal file
@@ -0,0 +1,196 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||||
|
%YAML 1.2
|
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|
---
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|
$id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
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|
$schema: http://devicetree.org/meta-schemas/core.yaml#
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|
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|
title: Broadcom STB USB PHY
|
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|
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|
description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
|
||||||
|
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|
maintainers:
|
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|
- Al Cooper <alcooperx@gmail.com>
|
||||||
|
- Rafał Miłecki <rafal@milecki.pl>
|
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|
|
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|
properties:
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|
compatible:
|
||||||
|
enum:
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||||||
|
- brcm,bcm4908-usb-phy
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|
- brcm,bcm7211-usb-phy
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|
- brcm,bcm7216-usb-phy
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|
- brcm,brcmstb-usb-phy
|
||||||
|
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||||||
|
reg:
|
||||||
|
minItems: 1
|
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|
maxItems: 6
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|
items:
|
||||||
|
- description: the base CTRL register
|
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|
- description: XHCI EC register
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|
- description: XHCI GBL register
|
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|
- description: USB PHY register
|
||||||
|
- description: USB MDIO register
|
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|
- description: BDC register
|
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|
|
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|
reg-names:
|
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|
minItems: 1
|
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|
maxItems: 6
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|
items:
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- const: ctrl
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- const: xhci_ec
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|
- const: xhci_gbl
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- const: usb_phy
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- const: usb_mdio
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- const: bdc_ec
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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- const: sw_usb
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- const: sw_usb3
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interrupts:
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description: wakeup interrupt
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interrupt-names:
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const: wake
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brcm,ipp:
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|
$ref: /schemas/types.yaml#/definitions/uint32
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description: Invert Port Power
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minimum: 0
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maximum: 1
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brcm,ioc:
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|
$ref: /schemas/types.yaml#/definitions/uint32
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|
description: Invert Over Current detection
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|
minimum: 0
|
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maximum: 1
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dr_mode:
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|
description: PHY Device mode. If this property is not defined, the PHY will
|
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|
default to "host" mode.
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|
enum:
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|
- host
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|
- peripheral
|
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|
- drd
|
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|
- typec-pd
|
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|
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|
brcm,syscon-piarbctl:
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|
description: phandle to syscon for handling config registers
|
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|
$ref: /schemas/types.yaml#/definitions/phandle
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|
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|
brcm,has-xhci:
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|
description: Indicates the PHY has an XHCI PHY.
|
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|
type: boolean
|
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|
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|
brcm,has-eohci:
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|
description: Indicates the PHY has an EHCI/OHCI PHY.
|
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|
type: boolean
|
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|
|
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|
"#phy-cells":
|
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|
description: |
|
||||||
|
Cell allows setting the type of the PHY. Possible values are:
|
||||||
|
- PHY_TYPE_USB2 for USB1.1/2.0 PHY
|
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|
- PHY_TYPE_USB3 for USB3.x PHY
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- reg
|
||||||
|
- "#phy-cells"
|
||||||
|
|
||||||
|
anyOf:
|
||||||
|
- required:
|
||||||
|
- brcm,has-xhci
|
||||||
|
- required:
|
||||||
|
- brcm,has-eohci
|
||||||
|
|
||||||
|
allOf:
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
enum:
|
||||||
|
- const: brcm,bcm4908-usb-phy
|
||||||
|
- const: brcm,brcmstb-usb-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 2
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
const: brcm,bcm7211-usb-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
minItems: 5
|
||||||
|
maxItems: 6
|
||||||
|
reg-names:
|
||||||
|
minItems: 5
|
||||||
|
maxItems: 6
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
const: brcm,bcm7216-usb-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
minItems: 3
|
||||||
|
maxItems: 3
|
||||||
|
reg-names:
|
||||||
|
minItems: 3
|
||||||
|
maxItems: 3
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
|
||||||
|
usb-phy@f0470200 {
|
||||||
|
compatible = "brcm,brcmstb-usb-phy";
|
||||||
|
reg = <0xf0470200 0xb8>,
|
||||||
|
<0xf0471940 0x6c0>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
dr_mode = "host";
|
||||||
|
brcm,ioc = <1>;
|
||||||
|
brcm,ipp = <1>;
|
||||||
|
brcm,has-xhci;
|
||||||
|
brcm,has-eohci;
|
||||||
|
clocks = <&usb20>, <&usb30>;
|
||||||
|
clock-names = "sw_usb", "sw_usb3";
|
||||||
|
};
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
|
||||||
|
usb-phy@29f0200 {
|
||||||
|
compatible = "brcm,bcm7211-usb-phy";
|
||||||
|
reg = <0x29f0200 0x200>,
|
||||||
|
<0x29c0880 0x30>,
|
||||||
|
<0x29cc100 0x534>,
|
||||||
|
<0x2808000 0x24>,
|
||||||
|
<0x2980080 0x8>;
|
||||||
|
reg-names = "ctrl",
|
||||||
|
"xhci_ec",
|
||||||
|
"xhci_gbl",
|
||||||
|
"usb_phy",
|
||||||
|
"usb_mdio";
|
||||||
|
brcm,ioc = <0x0>;
|
||||||
|
brcm,ipp = <0x0>;
|
||||||
|
interrupts = <0x30>;
|
||||||
|
interrupt-parent = <&vpu_intr1_nosec_intc>;
|
||||||
|
interrupt-names = "wake";
|
||||||
|
#phy-cells = <0x1>;
|
||||||
|
brcm,has-xhci;
|
||||||
|
brcm,syscon-piarbctl = <&syscon_piarbctl>;
|
||||||
|
clocks = <&scmi_clk 256>;
|
||||||
|
clock-names = "sw_usb";
|
||||||
|
};
|
||||||
85
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
Normal file
85
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
Normal file
@@ -0,0 +1,85 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
# Copyright (c) 2020 MediaTek
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||||
|
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||||
|
- Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||||
|
|
||||||
|
description: The MIPI DSI PHY supports up to 4-lane output.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
$nodename:
|
||||||
|
pattern: "^dsi-phy@[0-9a-f]+$"
|
||||||
|
|
||||||
|
compatible:
|
||||||
|
enum:
|
||||||
|
- mediatek,mt2701-mipi-tx
|
||||||
|
- mediatek,mt7623-mipi-tx
|
||||||
|
- mediatek,mt8173-mipi-tx
|
||||||
|
- mediatek,mt8183-mipi-tx
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: PLL reference clock
|
||||||
|
|
||||||
|
clock-output-names:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
"#phy-cells":
|
||||||
|
const: 0
|
||||||
|
|
||||||
|
"#clock-cells":
|
||||||
|
const: 0
|
||||||
|
|
||||||
|
nvmem-cells:
|
||||||
|
maxItems: 1
|
||||||
|
description: A phandle to the calibration data provided by a nvmem device,
|
||||||
|
if unspecified, default values shall be used.
|
||||||
|
|
||||||
|
nvmem-cell-names:
|
||||||
|
items:
|
||||||
|
- const: calibration-data
|
||||||
|
|
||||||
|
drive-strength-microamp:
|
||||||
|
description: adjust driving current
|
||||||
|
multipleOf: 200
|
||||||
|
minimum: 2000
|
||||||
|
maximum: 6000
|
||||||
|
default: 4600
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- clocks
|
||||||
|
- clock-output-names
|
||||||
|
- "#phy-cells"
|
||||||
|
- "#clock-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/clock/mt8173-clk.h>
|
||||||
|
dsi-phy@10215000 {
|
||||||
|
compatible = "mediatek,mt8173-mipi-tx";
|
||||||
|
reg = <0x10215000 0x1000>;
|
||||||
|
clocks = <&clk26m>;
|
||||||
|
clock-output-names = "mipi_tx0_pll";
|
||||||
|
drive-strength-microamp = <4000>;
|
||||||
|
nvmem-cells= <&mipi_tx_calibration>;
|
||||||
|
nvmem-cell-names = "calibration-data";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
#phy-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
92
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
Normal file
92
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
Normal file
@@ -0,0 +1,92 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
# Copyright (c) 2020 MediaTek
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||||
|
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||||
|
- Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
|
||||||
|
output and drives the HDMI pads.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
$nodename:
|
||||||
|
pattern: "^hdmi-phy@[0-9a-f]+$"
|
||||||
|
|
||||||
|
compatible:
|
||||||
|
enum:
|
||||||
|
- mediatek,mt2701-hdmi-phy
|
||||||
|
- mediatek,mt7623-hdmi-phy
|
||||||
|
- mediatek,mt8173-hdmi-phy
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: PLL reference clock
|
||||||
|
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: pll_ref
|
||||||
|
|
||||||
|
clock-output-names:
|
||||||
|
items:
|
||||||
|
- const: hdmitx_dig_cts
|
||||||
|
|
||||||
|
"#phy-cells":
|
||||||
|
const: 0
|
||||||
|
|
||||||
|
"#clock-cells":
|
||||||
|
const: 0
|
||||||
|
|
||||||
|
mediatek,ibias:
|
||||||
|
description:
|
||||||
|
TX DRV bias current for < 1.65Gbps
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 0
|
||||||
|
maximum: 63
|
||||||
|
default: 0xa
|
||||||
|
|
||||||
|
mediatek,ibias_up:
|
||||||
|
description:
|
||||||
|
TX DRV bias current for >= 1.65Gbps
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 0
|
||||||
|
maximum: 63
|
||||||
|
default: 0x1c
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- clocks
|
||||||
|
- clock-names
|
||||||
|
- clock-output-names
|
||||||
|
- "#phy-cells"
|
||||||
|
- "#clock-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/clock/mt8173-clk.h>
|
||||||
|
hdmi_phy: hdmi-phy@10209100 {
|
||||||
|
compatible = "mediatek,mt8173-hdmi-phy";
|
||||||
|
reg = <0x10209100 0x24>;
|
||||||
|
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
||||||
|
clock-names = "pll_ref";
|
||||||
|
clock-output-names = "hdmitx_dig_cts";
|
||||||
|
mediatek,ibias = <0xa>;
|
||||||
|
mediatek,ibias_up = <0x1c>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
#phy-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
260
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
Normal file
260
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
Normal file
@@ -0,0 +1,260 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
# Copyright (c) 2020 MediaTek
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: MediaTek T-PHY Controller Device Tree Bindings
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
The T-PHY controller supports physical layer functionality for a number of
|
||||||
|
controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
|
||||||
|
|
||||||
|
Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
|
||||||
|
T-PHY V2 (mt2712) when works on USB mode:
|
||||||
|
-----------------------------------
|
||||||
|
Version 1:
|
||||||
|
port offset bank
|
||||||
|
shared 0x0000 SPLLC
|
||||||
|
0x0100 FMREG
|
||||||
|
u2 port0 0x0800 U2PHY_COM
|
||||||
|
u3 port0 0x0900 U3PHYD
|
||||||
|
0x0a00 U3PHYD_BANK2
|
||||||
|
0x0b00 U3PHYA
|
||||||
|
0x0c00 U3PHYA_DA
|
||||||
|
u2 port1 0x1000 U2PHY_COM
|
||||||
|
u3 port1 0x1100 U3PHYD
|
||||||
|
0x1200 U3PHYD_BANK2
|
||||||
|
0x1300 U3PHYA
|
||||||
|
0x1400 U3PHYA_DA
|
||||||
|
u2 port2 0x1800 U2PHY_COM
|
||||||
|
...
|
||||||
|
|
||||||
|
Version 2:
|
||||||
|
port offset bank
|
||||||
|
u2 port0 0x0000 MISC
|
||||||
|
0x0100 FMREG
|
||||||
|
0x0300 U2PHY_COM
|
||||||
|
u3 port0 0x0700 SPLLC
|
||||||
|
0x0800 CHIP
|
||||||
|
0x0900 U3PHYD
|
||||||
|
0x0a00 U3PHYD_BANK2
|
||||||
|
0x0b00 U3PHYA
|
||||||
|
0x0c00 U3PHYA_DA
|
||||||
|
u2 port1 0x1000 MISC
|
||||||
|
0x1100 FMREG
|
||||||
|
0x1300 U2PHY_COM
|
||||||
|
u3 port1 0x1700 SPLLC
|
||||||
|
0x1800 CHIP
|
||||||
|
0x1900 U3PHYD
|
||||||
|
0x1a00 U3PHYD_BANK2
|
||||||
|
0x1b00 U3PHYA
|
||||||
|
0x1c00 U3PHYA_DA
|
||||||
|
u2 port2 0x2000 MISC
|
||||||
|
...
|
||||||
|
|
||||||
|
SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
|
||||||
|
into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
|
||||||
|
added on V2.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
$nodename:
|
||||||
|
pattern: "^t-phy@[0-9a-f]+$"
|
||||||
|
|
||||||
|
compatible:
|
||||||
|
oneOf:
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- mediatek,mt2701-tphy
|
||||||
|
- mediatek,mt7623-tphy
|
||||||
|
- mediatek,mt7622-tphy
|
||||||
|
- mediatek,mt8516-tphy
|
||||||
|
- const: mediatek,generic-tphy-v1
|
||||||
|
- items:
|
||||||
|
- enum:
|
||||||
|
- mediatek,mt2712-tphy
|
||||||
|
- mediatek,mt7629-tphy
|
||||||
|
- mediatek,mt8183-tphy
|
||||||
|
- const: mediatek,generic-tphy-v2
|
||||||
|
- const: mediatek,mt2701-u3phy
|
||||||
|
deprecated: true
|
||||||
|
- const: mediatek,mt2712-u3phy
|
||||||
|
deprecated: true
|
||||||
|
- const: mediatek,mt8173-u3phy
|
||||||
|
|
||||||
|
reg:
|
||||||
|
description:
|
||||||
|
Register shared by multiple ports, exclude port's private register.
|
||||||
|
It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
|
||||||
|
T-PHY V2, such as mt2712.
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
"#address-cells":
|
||||||
|
enum: [1, 2]
|
||||||
|
|
||||||
|
"#size-cells":
|
||||||
|
enum: [1, 2]
|
||||||
|
|
||||||
|
# Used with non-empty value if optional 'reg' is not provided.
|
||||||
|
# The format of the value is an arbitrary number of triplets of
|
||||||
|
# (child-bus-address, parent-bus-address, length).
|
||||||
|
ranges: true
|
||||||
|
|
||||||
|
mediatek,src-ref-clk-mhz:
|
||||||
|
description:
|
||||||
|
Frequency of reference clock for slew rate calibrate
|
||||||
|
default: 26
|
||||||
|
|
||||||
|
mediatek,src-coef:
|
||||||
|
description:
|
||||||
|
Coefficient for slew rate calibrate, depends on SoC process
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
default: 28
|
||||||
|
|
||||||
|
# Required child node:
|
||||||
|
patternProperties:
|
||||||
|
"^usb-phy@[0-9a-f]+$":
|
||||||
|
type: object
|
||||||
|
description:
|
||||||
|
A sub-node is required for each port the controller provides.
|
||||||
|
Address range information including the usual 'reg' property
|
||||||
|
is used inside these nodes to describe the controller's topology.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 2
|
||||||
|
items:
|
||||||
|
- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
|
||||||
|
- description: Reference clock of analog phy
|
||||||
|
description:
|
||||||
|
Uses both clocks if the clock of analog and digital phys are
|
||||||
|
separated, otherwise uses "ref" clock only if needed.
|
||||||
|
|
||||||
|
clock-names:
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 2
|
||||||
|
items:
|
||||||
|
- const: ref
|
||||||
|
- const: da_ref
|
||||||
|
|
||||||
|
"#phy-cells":
|
||||||
|
const: 1
|
||||||
|
description: |
|
||||||
|
The cells contain the following arguments.
|
||||||
|
|
||||||
|
- description: The PHY type
|
||||||
|
enum:
|
||||||
|
- PHY_TYPE_USB2
|
||||||
|
- PHY_TYPE_USB3
|
||||||
|
- PHY_TYPE_PCIE
|
||||||
|
- PHY_TYPE_SATA
|
||||||
|
|
||||||
|
# The following optional vendor properties are only for debug or HQA test
|
||||||
|
mediatek,eye-src:
|
||||||
|
description:
|
||||||
|
The value of slew rate calibrate (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,eye-vrt:
|
||||||
|
description:
|
||||||
|
The selection of VRT reference voltage (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,eye-term:
|
||||||
|
description:
|
||||||
|
The selection of HS_TX TERM reference voltage (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,intr:
|
||||||
|
description:
|
||||||
|
The selection of internal resistor (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 31
|
||||||
|
|
||||||
|
mediatek,discth:
|
||||||
|
description:
|
||||||
|
The selection of disconnect threshold (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 15
|
||||||
|
|
||||||
|
mediatek,bc12:
|
||||||
|
description:
|
||||||
|
Specify the flag to enable BC1.2 if support it
|
||||||
|
type: boolean
|
||||||
|
|
||||||
|
required:
|
||||||
|
- reg
|
||||||
|
- "#phy-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- "#address-cells"
|
||||||
|
- "#size-cells"
|
||||||
|
- ranges
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/clock/mt8173-clk.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
usb@11271000 {
|
||||||
|
compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
|
||||||
|
reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
|
||||||
|
reg-names = "mac", "ippc";
|
||||||
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||||
|
<&u3port0 PHY_TYPE_USB3>,
|
||||||
|
<&u2port1 PHY_TYPE_USB2>;
|
||||||
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&topckgen CLK_TOP_USB30_SEL>;
|
||||||
|
clock-names = "sys_ck";
|
||||||
|
};
|
||||||
|
|
||||||
|
t-phy@11290000 {
|
||||||
|
compatible = "mediatek,mt8173-u3phy";
|
||||||
|
reg = <0x11290000 0x800>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
u2port0: usb-phy@11290800 {
|
||||||
|
reg = <0x11290800 0x100>;
|
||||||
|
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
|
||||||
|
clock-names = "ref", "da_ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
u3port0: usb-phy@11290900 {
|
||||||
|
reg = <0x11290900 0x700>;
|
||||||
|
clocks = <&clk26m>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
u2port1: usb-phy@11291000 {
|
||||||
|
reg = <0x11291000 0x100>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
64
Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
Normal file
64
Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
Normal file
@@ -0,0 +1,64 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
# Copyright (c) 2020 MediaTek
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: MediaTek Universal Flash Storage (UFS) M-PHY binding
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Stanley Chu <stanley.chu@mediatek.com>
|
||||||
|
- Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
|
||||||
|
Each UFS M-PHY node should have its own node.
|
||||||
|
To bind UFS M-PHY with UFS host controller, the controller node should
|
||||||
|
contain a phandle reference to UFS M-PHY node.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
$nodename:
|
||||||
|
pattern: "^ufs-phy@[0-9a-f]+$"
|
||||||
|
|
||||||
|
compatible:
|
||||||
|
const: mediatek,mt8183-ufsphy
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: Unipro core control clock.
|
||||||
|
- description: M-PHY core control clock.
|
||||||
|
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: unipro
|
||||||
|
- const: mp
|
||||||
|
|
||||||
|
"#phy-cells":
|
||||||
|
const: 0
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- "#phy-cells"
|
||||||
|
- clocks
|
||||||
|
- clock-names
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/clock/mt8183-clk.h>
|
||||||
|
ufsphy: ufs-phy@11fa0000 {
|
||||||
|
compatible = "mediatek,mt8183-ufsphy";
|
||||||
|
reg = <0x11fa0000 0xc000>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
|
||||||
|
<&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
|
||||||
|
clock-names = "unipro", "mp";
|
||||||
|
#phy-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
199
Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
Normal file
199
Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
Normal file
@@ -0,0 +1,199 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
# Copyright (c) 2020 MediaTek
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: MediaTek XS-PHY Controller Device Tree Bindings
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
The XS-PHY controller supports physical layer functionality for USB3.1
|
||||||
|
GEN2 controller on MediaTek SoCs.
|
||||||
|
|
||||||
|
Banks layout of xsphy
|
||||||
|
----------------------------------
|
||||||
|
port offset bank
|
||||||
|
u2 port0 0x0000 MISC
|
||||||
|
0x0100 FMREG
|
||||||
|
0x0300 U2PHY_COM
|
||||||
|
u2 port1 0x1000 MISC
|
||||||
|
0x1100 FMREG
|
||||||
|
0x1300 U2PHY_COM
|
||||||
|
u2 port2 0x2000 MISC
|
||||||
|
...
|
||||||
|
u31 common 0x3000 DIG_GLB
|
||||||
|
0x3100 PHYA_GLB
|
||||||
|
u31 port0 0x3400 DIG_LN_TOP
|
||||||
|
0x3500 DIG_LN_TX0
|
||||||
|
0x3600 DIG_LN_RX0
|
||||||
|
0x3700 DIG_LN_DAIF
|
||||||
|
0x3800 PHYA_LN
|
||||||
|
u31 port1 0x3a00 DIG_LN_TOP
|
||||||
|
0x3b00 DIG_LN_TX0
|
||||||
|
0x3c00 DIG_LN_RX0
|
||||||
|
0x3d00 DIG_LN_DAIF
|
||||||
|
0x3e00 PHYA_LN
|
||||||
|
...
|
||||||
|
DIG_GLB & PHYA_GLB are shared by U31 ports.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
$nodename:
|
||||||
|
pattern: "^xs-phy@[0-9a-f]+$"
|
||||||
|
|
||||||
|
compatible:
|
||||||
|
items:
|
||||||
|
- enum:
|
||||||
|
- mediatek,mt3611-xsphy
|
||||||
|
- mediatek,mt3612-xsphy
|
||||||
|
- const: mediatek,xsphy
|
||||||
|
|
||||||
|
reg:
|
||||||
|
description:
|
||||||
|
Register shared by multiple U3 ports, exclude port's private register,
|
||||||
|
if only U2 ports provided, shouldn't use the property.
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
"#address-cells":
|
||||||
|
enum: [1, 2]
|
||||||
|
|
||||||
|
"#size-cells":
|
||||||
|
enum: [1, 2]
|
||||||
|
|
||||||
|
ranges: true
|
||||||
|
|
||||||
|
mediatek,src-ref-clk-mhz:
|
||||||
|
description:
|
||||||
|
Frequency of reference clock for slew rate calibrate
|
||||||
|
default: 26
|
||||||
|
|
||||||
|
mediatek,src-coef:
|
||||||
|
description:
|
||||||
|
Coefficient for slew rate calibrate, depends on SoC process
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
default: 17
|
||||||
|
|
||||||
|
# Required child node:
|
||||||
|
patternProperties:
|
||||||
|
"^usb-phy@[0-9a-f]+$":
|
||||||
|
type: object
|
||||||
|
description:
|
||||||
|
A sub-node is required for each port the controller provides.
|
||||||
|
Address range information including the usual 'reg' property
|
||||||
|
is used inside these nodes to describe the controller's topology.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
|
||||||
|
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: ref
|
||||||
|
|
||||||
|
"#phy-cells":
|
||||||
|
const: 1
|
||||||
|
description: |
|
||||||
|
The cells contain the following arguments.
|
||||||
|
|
||||||
|
- description: The PHY type
|
||||||
|
enum:
|
||||||
|
- PHY_TYPE_USB2
|
||||||
|
- PHY_TYPE_USB3
|
||||||
|
|
||||||
|
# The following optional vendor properties are only for debug or HQA test
|
||||||
|
mediatek,eye-src:
|
||||||
|
description:
|
||||||
|
The value of slew rate calibrate (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,eye-vrt:
|
||||||
|
description:
|
||||||
|
The selection of VRT reference voltage (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,eye-term:
|
||||||
|
description:
|
||||||
|
The selection of HS_TX TERM reference voltage (U2 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 7
|
||||||
|
|
||||||
|
mediatek,efuse-intr:
|
||||||
|
description:
|
||||||
|
The selection of Internal Resistor (U2/U3 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 63
|
||||||
|
|
||||||
|
mediatek,efuse-tx-imp:
|
||||||
|
description:
|
||||||
|
The selection of TX Impedance (U3 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 31
|
||||||
|
|
||||||
|
mediatek,efuse-rx-imp:
|
||||||
|
description:
|
||||||
|
The selection of RX Impedance (U3 phy)
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 31
|
||||||
|
|
||||||
|
required:
|
||||||
|
- reg
|
||||||
|
- clocks
|
||||||
|
- clock-names
|
||||||
|
- "#phy-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- "#address-cells"
|
||||||
|
- "#size-cells"
|
||||||
|
- ranges
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
|
||||||
|
u3phy: xs-phy@11c40000 {
|
||||||
|
compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
|
||||||
|
reg = <0x11c43000 0x0200>;
|
||||||
|
mediatek,src-ref-clk-mhz = <26>;
|
||||||
|
mediatek,src-coef = <17>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
u2port0: usb-phy@11c40000 {
|
||||||
|
reg = <0x11c40000 0x0400>;
|
||||||
|
clocks = <&clk48m>;
|
||||||
|
clock-names = "ref";
|
||||||
|
mediatek,eye-src = <4>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
u3port0: usb-phy@11c43000 {
|
||||||
|
reg = <0x11c43400 0x0500>;
|
||||||
|
clocks = <&clk26m>;
|
||||||
|
clock-names = "ref";
|
||||||
|
mediatek,efuse-intr = <28>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
...
|
||||||
@@ -1,162 +0,0 @@
|
|||||||
MediaTek T-PHY binding
|
|
||||||
--------------------------
|
|
||||||
|
|
||||||
T-phy controller supports physical layer functionality for a number of
|
|
||||||
controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
|
|
||||||
|
|
||||||
Required properties (controller (parent) node):
|
|
||||||
- compatible : should be one of
|
|
||||||
"mediatek,generic-tphy-v1"
|
|
||||||
"mediatek,generic-tphy-v2"
|
|
||||||
"mediatek,mt2701-u3phy" (deprecated)
|
|
||||||
"mediatek,mt2712-u3phy" (deprecated)
|
|
||||||
"mediatek,mt8173-u3phy";
|
|
||||||
make use of "mediatek,generic-tphy-v1" on mt2701 instead and
|
|
||||||
"mediatek,generic-tphy-v2" on mt2712 instead.
|
|
||||||
|
|
||||||
- #address-cells: the number of cells used to represent physical
|
|
||||||
base addresses.
|
|
||||||
- #size-cells: the number of cells used to represent the size of an address.
|
|
||||||
- ranges: the address mapping relationship to the parent, defined with
|
|
||||||
- empty value: if optional 'reg' is used.
|
|
||||||
- non-empty value: if optional 'reg' is not used. should set
|
|
||||||
the child's base address to 0, the physical address
|
|
||||||
within parent's address space, and the length of
|
|
||||||
the address map.
|
|
||||||
|
|
||||||
Required nodes : a sub-node is required for each port the controller
|
|
||||||
provides. Address range information including the usual
|
|
||||||
'reg' property is used inside these nodes to describe
|
|
||||||
the controller's topology.
|
|
||||||
|
|
||||||
Optional properties (controller (parent) node):
|
|
||||||
- reg : offset and length of register shared by multiple ports,
|
|
||||||
exclude port's private register. It is needed on mt2701
|
|
||||||
and mt8173, but not on mt2712.
|
|
||||||
- mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
|
|
||||||
calibrate
|
|
||||||
- mediatek,src-coef : coefficient for slew rate calibrate, depends on
|
|
||||||
SoC process
|
|
||||||
|
|
||||||
Required properties (port (child) node):
|
|
||||||
- reg : address and length of the register set for the port.
|
|
||||||
- #phy-cells : should be 1 (See second example)
|
|
||||||
cell after port phandle is phy type from:
|
|
||||||
- PHY_TYPE_USB2
|
|
||||||
- PHY_TYPE_USB3
|
|
||||||
- PHY_TYPE_PCIE
|
|
||||||
- PHY_TYPE_SATA
|
|
||||||
|
|
||||||
Optional properties (PHY_TYPE_USB2 port (child) node):
|
|
||||||
- clocks : a list of phandle + clock-specifier pairs, one for each
|
|
||||||
entry in clock-names
|
|
||||||
- clock-names : may contain
|
|
||||||
"ref": 48M reference clock for HighSpeed (digital) phy; and 26M
|
|
||||||
reference clock for SuperSpeed (digital) phy, sometimes is
|
|
||||||
24M, 25M or 27M, depended on platform.
|
|
||||||
"da_ref": the reference clock of analog phy, used if the clocks
|
|
||||||
of analog and digital phys are separated, otherwise uses
|
|
||||||
"ref" clock only if needed.
|
|
||||||
|
|
||||||
- mediatek,eye-src : u32, the value of slew rate calibrate
|
|
||||||
- mediatek,eye-vrt : u32, the selection of VRT reference voltage
|
|
||||||
- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
|
|
||||||
- mediatek,bc12 : bool, enable BC12 of u2phy if support it
|
|
||||||
- mediatek,discth : u32, the selection of disconnect threshold
|
|
||||||
- mediatek,intr : u32, the selection of internal R (resistance)
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
u3phy: usb-phy@11290000 {
|
|
||||||
compatible = "mediatek,mt8173-u3phy";
|
|
||||||
reg = <0 0x11290000 0 0x800>;
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
u2port0: usb-phy@11290800 {
|
|
||||||
reg = <0 0x11290800 0 0x100>;
|
|
||||||
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
|
||||||
clock-names = "ref";
|
|
||||||
#phy-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
u3port0: usb-phy@11290900 {
|
|
||||||
reg = <0 0x11290800 0 0x700>;
|
|
||||||
clocks = <&clk26m>;
|
|
||||||
clock-names = "ref";
|
|
||||||
#phy-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
u2port1: usb-phy@11291000 {
|
|
||||||
reg = <0 0x11291000 0 0x100>;
|
|
||||||
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
|
||||||
clock-names = "ref";
|
|
||||||
#phy-cells = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
Specifying phy control of devices
|
|
||||||
---------------------------------
|
|
||||||
|
|
||||||
Device nodes should specify the configuration required in their "phys"
|
|
||||||
property, containing a phandle to the phy port node and a device type;
|
|
||||||
phy-names for each port are optional.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
#include <dt-bindings/phy/phy.h>
|
|
||||||
|
|
||||||
usb30: usb@11270000 {
|
|
||||||
...
|
|
||||||
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
|
||||||
phy-names = "usb2-0", "usb3-0";
|
|
||||||
...
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
Layout differences of banks between mt8173/mt2701 and mt2712
|
|
||||||
-------------------------------------------------------------
|
|
||||||
mt8173 and mt2701:
|
|
||||||
port offset bank
|
|
||||||
shared 0x0000 SPLLC
|
|
||||||
0x0100 FMREG
|
|
||||||
u2 port0 0x0800 U2PHY_COM
|
|
||||||
u3 port0 0x0900 U3PHYD
|
|
||||||
0x0a00 U3PHYD_BANK2
|
|
||||||
0x0b00 U3PHYA
|
|
||||||
0x0c00 U3PHYA_DA
|
|
||||||
u2 port1 0x1000 U2PHY_COM
|
|
||||||
u3 port1 0x1100 U3PHYD
|
|
||||||
0x1200 U3PHYD_BANK2
|
|
||||||
0x1300 U3PHYA
|
|
||||||
0x1400 U3PHYA_DA
|
|
||||||
u2 port2 0x1800 U2PHY_COM
|
|
||||||
...
|
|
||||||
|
|
||||||
mt2712:
|
|
||||||
port offset bank
|
|
||||||
u2 port0 0x0000 MISC
|
|
||||||
0x0100 FMREG
|
|
||||||
0x0300 U2PHY_COM
|
|
||||||
u3 port0 0x0700 SPLLC
|
|
||||||
0x0800 CHIP
|
|
||||||
0x0900 U3PHYD
|
|
||||||
0x0a00 U3PHYD_BANK2
|
|
||||||
0x0b00 U3PHYA
|
|
||||||
0x0c00 U3PHYA_DA
|
|
||||||
u2 port1 0x1000 MISC
|
|
||||||
0x1100 FMREG
|
|
||||||
0x1300 U2PHY_COM
|
|
||||||
u3 port1 0x1700 SPLLC
|
|
||||||
0x1800 CHIP
|
|
||||||
0x1900 U3PHYD
|
|
||||||
0x1a00 U3PHYD_BANK2
|
|
||||||
0x1b00 U3PHYA
|
|
||||||
0x1c00 U3PHYA_DA
|
|
||||||
u2 port2 0x2000 MISC
|
|
||||||
...
|
|
||||||
|
|
||||||
SPLLC shared by u3 ports and FMREG shared by u2 ports on
|
|
||||||
mt8173/mt2701 are put back into each port; a new bank MISC for
|
|
||||||
u2 ports and CHIP for u3 ports are added on mt2712.
|
|
||||||
@@ -1,38 +0,0 @@
|
|||||||
MediaTek Universal Flash Storage (UFS) M-PHY binding
|
|
||||||
--------------------------------------------------------
|
|
||||||
|
|
||||||
UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
|
|
||||||
Each UFS M-PHY node should have its own node.
|
|
||||||
|
|
||||||
To bind UFS M-PHY with UFS host controller, the controller node should
|
|
||||||
contain a phandle reference to UFS M-PHY node.
|
|
||||||
|
|
||||||
Required properties for UFS M-PHY nodes:
|
|
||||||
- compatible : Compatible list, contains the following controller:
|
|
||||||
"mediatek,mt8183-ufsphy" for ufs phy
|
|
||||||
persent on MT81xx chipsets.
|
|
||||||
- reg : Address and length of the UFS M-PHY register set.
|
|
||||||
- #phy-cells : This property shall be set to 0.
|
|
||||||
- clocks : List of phandle and clock specifier pairs.
|
|
||||||
- clock-names : List of clock input name strings sorted in the same
|
|
||||||
order as the clocks property. Following clocks are
|
|
||||||
mandatory.
|
|
||||||
"unipro": Unipro core control clock.
|
|
||||||
"mp": M-PHY core control clock.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
ufsphy: phy@11fa0000 {
|
|
||||||
compatible = "mediatek,mt8183-ufsphy";
|
|
||||||
reg = <0 0x11fa0000 0 0xc000>;
|
|
||||||
#phy-cells = <0>;
|
|
||||||
|
|
||||||
clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
|
|
||||||
<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
|
|
||||||
clock-names = "unipro", "mp";
|
|
||||||
};
|
|
||||||
|
|
||||||
ufshci@11270000 {
|
|
||||||
...
|
|
||||||
phys = <&ufsphy>;
|
|
||||||
};
|
|
||||||
@@ -1,109 +0,0 @@
|
|||||||
MediaTek XS-PHY binding
|
|
||||||
--------------------------
|
|
||||||
|
|
||||||
The XS-PHY controller supports physical layer functionality for USB3.1
|
|
||||||
GEN2 controller on MediaTek SoCs.
|
|
||||||
|
|
||||||
Required properties (controller (parent) node):
|
|
||||||
- compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
|
|
||||||
soc-model is the name of SoC, such as mt3611 etc;
|
|
||||||
when using "mediatek,xsphy" compatible string, you need SoC specific
|
|
||||||
ones in addition, one of:
|
|
||||||
- "mediatek,mt3611-xsphy"
|
|
||||||
|
|
||||||
- #address-cells, #size-cells : should use the same values as the root node
|
|
||||||
- ranges: must be present
|
|
||||||
|
|
||||||
Optional properties (controller (parent) node):
|
|
||||||
- reg : offset and length of register shared by multiple U3 ports,
|
|
||||||
exclude port's private register, if only U2 ports provided,
|
|
||||||
shouldn't use the property.
|
|
||||||
- mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
|
|
||||||
calibrate
|
|
||||||
- mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
|
|
||||||
SoC process
|
|
||||||
|
|
||||||
Required nodes : a sub-node is required for each port the controller
|
|
||||||
provides. Address range information including the usual
|
|
||||||
'reg' property is used inside these nodes to describe
|
|
||||||
the controller's topology.
|
|
||||||
|
|
||||||
Required properties (port (child) node):
|
|
||||||
- reg : address and length of the register set for the port.
|
|
||||||
- clocks : a list of phandle + clock-specifier pairs, one for each
|
|
||||||
entry in clock-names
|
|
||||||
- clock-names : must contain
|
|
||||||
"ref": 48M reference clock for HighSpeed analog phy; and 26M
|
|
||||||
reference clock for SuperSpeedPlus analog phy, sometimes is
|
|
||||||
24M, 25M or 27M, depended on platform.
|
|
||||||
- #phy-cells : should be 1
|
|
||||||
cell after port phandle is phy type from:
|
|
||||||
- PHY_TYPE_USB2
|
|
||||||
- PHY_TYPE_USB3
|
|
||||||
|
|
||||||
The following optional properties are only for debug or HQA test
|
|
||||||
Optional properties (PHY_TYPE_USB2 port (child) node):
|
|
||||||
- mediatek,eye-src : u32, the value of slew rate calibrate
|
|
||||||
- mediatek,eye-vrt : u32, the selection of VRT reference voltage
|
|
||||||
- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
|
|
||||||
- mediatek,efuse-intr : u32, the selection of Internal Resistor
|
|
||||||
|
|
||||||
Optional properties (PHY_TYPE_USB3 port (child) node):
|
|
||||||
- mediatek,efuse-intr : u32, the selection of Internal Resistor
|
|
||||||
- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
|
|
||||||
- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
|
|
||||||
|
|
||||||
Banks layout of xsphy
|
|
||||||
-------------------------------------------------------------
|
|
||||||
port offset bank
|
|
||||||
u2 port0 0x0000 MISC
|
|
||||||
0x0100 FMREG
|
|
||||||
0x0300 U2PHY_COM
|
|
||||||
u2 port1 0x1000 MISC
|
|
||||||
0x1100 FMREG
|
|
||||||
0x1300 U2PHY_COM
|
|
||||||
u2 port2 0x2000 MISC
|
|
||||||
...
|
|
||||||
u31 common 0x3000 DIG_GLB
|
|
||||||
0x3100 PHYA_GLB
|
|
||||||
u31 port0 0x3400 DIG_LN_TOP
|
|
||||||
0x3500 DIG_LN_TX0
|
|
||||||
0x3600 DIG_LN_RX0
|
|
||||||
0x3700 DIG_LN_DAIF
|
|
||||||
0x3800 PHYA_LN
|
|
||||||
u31 port1 0x3a00 DIG_LN_TOP
|
|
||||||
0x3b00 DIG_LN_TX0
|
|
||||||
0x3c00 DIG_LN_RX0
|
|
||||||
0x3d00 DIG_LN_DAIF
|
|
||||||
0x3e00 PHYA_LN
|
|
||||||
...
|
|
||||||
|
|
||||||
DIG_GLB & PHYA_GLB are shared by U31 ports.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
u3phy: usb-phy@11c40000 {
|
|
||||||
compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
|
|
||||||
reg = <0 0x11c43000 0 0x0200>;
|
|
||||||
mediatek,src-ref-clk-mhz = <26>;
|
|
||||||
mediatek,src-coef = <17>;
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
u2port0: usb-phy@11c40000 {
|
|
||||||
reg = <0 0x11c40000 0 0x0400>;
|
|
||||||
clocks = <&clk48m>;
|
|
||||||
clock-names = "ref";
|
|
||||||
mediatek,eye-src = <4>;
|
|
||||||
#phy-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
u3port0: usb-phy@11c43000 {
|
|
||||||
reg = <0 0x11c43400 0 0x0500>;
|
|
||||||
clocks = <&clk26m>;
|
|
||||||
clock-names = "ref";
|
|
||||||
mediatek,efuse-intr = <28>;
|
|
||||||
#phy-cells = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@@ -45,6 +45,12 @@ properties:
|
|||||||
"#size-cells":
|
"#size-cells":
|
||||||
const: 0
|
const: 0
|
||||||
|
|
||||||
|
vdda1v1-supply:
|
||||||
|
description: regulator providing 1V1 power supply to the PLL block
|
||||||
|
|
||||||
|
vdda1v8-supply:
|
||||||
|
description: regulator providing 1V8 power supply to the PLL block
|
||||||
|
|
||||||
#Required child nodes:
|
#Required child nodes:
|
||||||
|
|
||||||
patternProperties:
|
patternProperties:
|
||||||
@@ -61,12 +67,6 @@ patternProperties:
|
|||||||
phy-supply:
|
phy-supply:
|
||||||
description: regulator providing 3V3 power supply to the PHY.
|
description: regulator providing 3V3 power supply to the PHY.
|
||||||
|
|
||||||
vdda1v1-supply:
|
|
||||||
description: regulator providing 1V1 power supply to the PLL block
|
|
||||||
|
|
||||||
vdda1v8-supply:
|
|
||||||
description: regulator providing 1V8 power supply to the PLL block
|
|
||||||
|
|
||||||
"#phy-cells":
|
"#phy-cells":
|
||||||
enum: [ 0x0, 0x1 ]
|
enum: [ 0x0, 0x1 ]
|
||||||
|
|
||||||
@@ -90,8 +90,6 @@ patternProperties:
|
|||||||
required:
|
required:
|
||||||
- reg
|
- reg
|
||||||
- phy-supply
|
- phy-supply
|
||||||
- vdda1v1-supply
|
|
||||||
- vdda1v8-supply
|
|
||||||
- "#phy-cells"
|
- "#phy-cells"
|
||||||
|
|
||||||
additionalProperties: false
|
additionalProperties: false
|
||||||
@@ -102,6 +100,8 @@ required:
|
|||||||
- clocks
|
- clocks
|
||||||
- "#address-cells"
|
- "#address-cells"
|
||||||
- "#size-cells"
|
- "#size-cells"
|
||||||
|
- vdda1v1-supply
|
||||||
|
- vdda1v8-supply
|
||||||
- usb-phy@0
|
- usb-phy@0
|
||||||
- usb-phy@1
|
- usb-phy@1
|
||||||
|
|
||||||
@@ -116,22 +116,20 @@ examples:
|
|||||||
reg = <0x5a006000 0x1000>;
|
reg = <0x5a006000 0x1000>;
|
||||||
clocks = <&rcc USBPHY_K>;
|
clocks = <&rcc USBPHY_K>;
|
||||||
resets = <&rcc USBPHY_R>;
|
resets = <&rcc USBPHY_R>;
|
||||||
|
vdda1v1-supply = <®11>;
|
||||||
|
vdda1v8-supply = <®18>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
usbphyc_port0: usb-phy@0 {
|
usbphyc_port0: usb-phy@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
phy-supply = <&vdd_usb>;
|
phy-supply = <&vdd_usb>;
|
||||||
vdda1v1-supply = <®11>;
|
|
||||||
vdda1v8-supply = <®18>;
|
|
||||||
#phy-cells = <0>;
|
#phy-cells = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
usbphyc_port1: usb-phy@1 {
|
usbphyc_port1: usb-phy@1 {
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
phy-supply = <&vdd_usb>;
|
phy-supply = <&vdd_usb>;
|
||||||
vdda1v1-supply = <®11>;
|
|
||||||
vdda1v8-supply = <®18>;
|
|
||||||
#phy-cells = <1>;
|
#phy-cells = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|||||||
@@ -25,19 +25,32 @@ properties:
|
|||||||
- qcom,msm8998-qmp-pcie-phy
|
- qcom,msm8998-qmp-pcie-phy
|
||||||
- qcom,msm8998-qmp-ufs-phy
|
- qcom,msm8998-qmp-ufs-phy
|
||||||
- qcom,msm8998-qmp-usb3-phy
|
- qcom,msm8998-qmp-usb3-phy
|
||||||
|
- qcom,sc8180x-qmp-ufs-phy
|
||||||
|
- qcom,sc8180x-qmp-usb3-phy
|
||||||
- qcom,sdm845-qhp-pcie-phy
|
- qcom,sdm845-qhp-pcie-phy
|
||||||
- qcom,sdm845-qmp-pcie-phy
|
- qcom,sdm845-qmp-pcie-phy
|
||||||
- qcom,sdm845-qmp-ufs-phy
|
- qcom,sdm845-qmp-ufs-phy
|
||||||
- qcom,sdm845-qmp-usb3-uni-phy
|
- qcom,sdm845-qmp-usb3-uni-phy
|
||||||
- qcom,sm8150-qmp-ufs-phy
|
- qcom,sm8150-qmp-ufs-phy
|
||||||
|
- qcom,sm8150-qmp-usb3-phy
|
||||||
|
- qcom,sm8150-qmp-usb3-uni-phy
|
||||||
- qcom,sm8250-qmp-ufs-phy
|
- qcom,sm8250-qmp-ufs-phy
|
||||||
- qcom,sm8250-qmp-gen3x1-pcie-phy
|
- qcom,sm8250-qmp-gen3x1-pcie-phy
|
||||||
- qcom,sm8250-qmp-gen3x2-pcie-phy
|
- qcom,sm8250-qmp-gen3x2-pcie-phy
|
||||||
- qcom,sm8250-qmp-modem-pcie-phy
|
- qcom,sm8250-qmp-modem-pcie-phy
|
||||||
|
- qcom,sm8250-qmp-usb3-phy
|
||||||
|
- qcom,sm8250-qmp-usb3-uni-phy
|
||||||
|
- qcom,sm8350-qmp-ufs-phy
|
||||||
|
- qcom,sm8350-qmp-usb3-phy
|
||||||
|
- qcom,sm8350-qmp-usb3-uni-phy
|
||||||
|
- qcom,sdx55-qmp-usb3-uni-phy
|
||||||
|
|
||||||
reg:
|
reg:
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 2
|
||||||
items:
|
items:
|
||||||
- description: Address and length of PHY's common serdes block.
|
- description: Address and length of PHY's common serdes block.
|
||||||
|
- description: Address and length of PHY's DP_COM control block.
|
||||||
|
|
||||||
"#clock-cells":
|
"#clock-cells":
|
||||||
enum: [ 1, 2 ]
|
enum: [ 1, 2 ]
|
||||||
@@ -131,6 +144,32 @@ allOf:
|
|||||||
items:
|
items:
|
||||||
- const: phy
|
- const: phy
|
||||||
- const: common
|
- const: common
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
enum:
|
||||||
|
- qcom,sdx55-qmp-usb3-uni-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: Phy aux clock.
|
||||||
|
- description: Phy config clock.
|
||||||
|
- description: 19.2 MHz ref clk.
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: aux
|
||||||
|
- const: cfg_ahb
|
||||||
|
- const: ref
|
||||||
|
resets:
|
||||||
|
items:
|
||||||
|
- description: reset of phy block.
|
||||||
|
- description: phy common block reset.
|
||||||
|
reset-names:
|
||||||
|
items:
|
||||||
|
- const: phy
|
||||||
|
- const: common
|
||||||
- if:
|
- if:
|
||||||
properties:
|
properties:
|
||||||
compatible:
|
compatible:
|
||||||
@@ -285,6 +324,64 @@ allOf:
|
|||||||
reset-names:
|
reset-names:
|
||||||
items:
|
items:
|
||||||
- const: phy
|
- const: phy
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
enum:
|
||||||
|
- qcom,sm8150-qmp-usb3-phy
|
||||||
|
- qcom,sm8150-qmp-usb3-uni-phy
|
||||||
|
- qcom,sm8250-qmp-usb3-uni-phy
|
||||||
|
- qcom,sm8350-qmp-usb3-uni-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: Phy aux clock.
|
||||||
|
- description: 19.2 MHz ref clk source.
|
||||||
|
- description: 19.2 MHz ref clk.
|
||||||
|
- description: Phy common block aux clock.
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: aux
|
||||||
|
- const: ref_clk_src
|
||||||
|
- const: ref
|
||||||
|
- const: com_aux
|
||||||
|
resets:
|
||||||
|
items:
|
||||||
|
- description: reset of phy block.
|
||||||
|
- description: phy common block reset.
|
||||||
|
reset-names:
|
||||||
|
items:
|
||||||
|
- const: phy
|
||||||
|
- const: common
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
contains:
|
||||||
|
enum:
|
||||||
|
- qcom,sm8250-qmp-usb3-phy
|
||||||
|
- qcom,sm8350-qmp-usb3-phy
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
clocks:
|
||||||
|
items:
|
||||||
|
- description: Phy aux clock.
|
||||||
|
- description: 19.2 MHz ref clk.
|
||||||
|
- description: Phy common block aux clock.
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: aux
|
||||||
|
- const: ref_clk_src
|
||||||
|
- const: com_aux
|
||||||
|
resets:
|
||||||
|
items:
|
||||||
|
- description: reset of phy block.
|
||||||
|
- description: phy common block reset.
|
||||||
|
reset-names:
|
||||||
|
items:
|
||||||
|
- const: phy
|
||||||
|
- const: common
|
||||||
|
|
||||||
examples:
|
examples:
|
||||||
- |
|
- |
|
||||||
|
|||||||
@@ -21,6 +21,8 @@ properties:
|
|||||||
- qcom,ipq8074-qusb2-phy
|
- qcom,ipq8074-qusb2-phy
|
||||||
- qcom,msm8996-qusb2-phy
|
- qcom,msm8996-qusb2-phy
|
||||||
- qcom,msm8998-qusb2-phy
|
- qcom,msm8998-qusb2-phy
|
||||||
|
- qcom,sdm660-qusb2-phy
|
||||||
|
- qcom,ipq6018-qusb2-phy
|
||||||
- items:
|
- items:
|
||||||
- enum:
|
- enum:
|
||||||
- qcom,sc7180-qusb2-phy
|
- qcom,sc7180-qusb2-phy
|
||||||
|
|||||||
@@ -16,6 +16,7 @@ properties:
|
|||||||
compatible:
|
compatible:
|
||||||
enum:
|
enum:
|
||||||
- qcom,usb-hs-28nm-femtophy
|
- qcom,usb-hs-28nm-femtophy
|
||||||
|
- qcom,usb-hs-28nm-mdm9607
|
||||||
|
|
||||||
reg:
|
reg:
|
||||||
maxItems: 1
|
maxItems: 1
|
||||||
|
|||||||
@@ -17,6 +17,8 @@ properties:
|
|||||||
enum:
|
enum:
|
||||||
- qcom,usb-snps-hs-7nm-phy
|
- qcom,usb-snps-hs-7nm-phy
|
||||||
- qcom,sm8150-usb-hs-phy
|
- qcom,sm8150-usb-hs-phy
|
||||||
|
- qcom,sm8250-usb-hs-phy
|
||||||
|
- qcom,sm8350-usb-hs-phy
|
||||||
- qcom,usb-snps-femto-v2-phy
|
- qcom,usb-snps-femto-v2-phy
|
||||||
|
|
||||||
reg:
|
reg:
|
||||||
|
|||||||
@@ -151,7 +151,7 @@ patternProperties:
|
|||||||
WIZ node should have '1' subnode for the SERDES. It could be either
|
WIZ node should have '1' subnode for the SERDES. It could be either
|
||||||
Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
|
Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
|
||||||
bindings specified in
|
bindings specified in
|
||||||
Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
|
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
|
||||||
Torrent SERDES should follow the bindings specified in
|
Torrent SERDES should follow the bindings specified in
|
||||||
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
|
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
|
||||||
|
|
||||||
|
|||||||
@@ -91,10 +91,11 @@ config PHY_BRCM_SATA
|
|||||||
|
|
||||||
config PHY_BRCM_USB
|
config PHY_BRCM_USB
|
||||||
tristate "Broadcom STB USB PHY driver"
|
tristate "Broadcom STB USB PHY driver"
|
||||||
depends on ARCH_BRCMSTB || COMPILE_TEST
|
depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST
|
||||||
depends on OF
|
depends on OF
|
||||||
select GENERIC_PHY
|
select GENERIC_PHY
|
||||||
select SOC_BRCMSTB
|
select SOC_BRCMSTB
|
||||||
|
default ARCH_BCM4908
|
||||||
default ARCH_BRCMSTB
|
default ARCH_BRCMSTB
|
||||||
help
|
help
|
||||||
Enable this to support the Broadcom STB USB PHY.
|
Enable this to support the Broadcom STB USB PHY.
|
||||||
|
|||||||
@@ -11,6 +11,7 @@
|
|||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
#include <linux/phy/phy.h>
|
#include <linux/phy/phy.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/interrupt.h>
|
#include <linux/interrupt.h>
|
||||||
@@ -34,7 +35,7 @@ struct value_to_name_map {
|
|||||||
};
|
};
|
||||||
|
|
||||||
struct match_chip_info {
|
struct match_chip_info {
|
||||||
void *init_func;
|
void (*init_func)(struct brcm_usb_init_params *params);
|
||||||
u8 required_regs[BRCM_REGS_MAX + 1];
|
u8 required_regs[BRCM_REGS_MAX + 1];
|
||||||
u8 optional_reg;
|
u8 optional_reg;
|
||||||
};
|
};
|
||||||
@@ -285,6 +286,10 @@ static const struct match_chip_info chip_info_7445 = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
static const struct of_device_id brcm_usb_dt_ids[] = {
|
static const struct of_device_id brcm_usb_dt_ids[] = {
|
||||||
|
{
|
||||||
|
.compatible = "brcm,bcm4908-usb-phy",
|
||||||
|
.data = &chip_info_7445,
|
||||||
|
},
|
||||||
{
|
{
|
||||||
.compatible = "brcm,bcm7216-usb-phy",
|
.compatible = "brcm,bcm7216-usb-phy",
|
||||||
.data = &chip_info_7216,
|
.data = &chip_info_7216,
|
||||||
@@ -427,8 +432,6 @@ static int brcm_usb_phy_probe(struct platform_device *pdev)
|
|||||||
struct device_node *dn = pdev->dev.of_node;
|
struct device_node *dn = pdev->dev.of_node;
|
||||||
int err;
|
int err;
|
||||||
const char *mode;
|
const char *mode;
|
||||||
const struct of_device_id *match;
|
|
||||||
void (*dvr_init)(struct brcm_usb_init_params *params);
|
|
||||||
const struct match_chip_info *info;
|
const struct match_chip_info *info;
|
||||||
struct regmap *rmap;
|
struct regmap *rmap;
|
||||||
int x;
|
int x;
|
||||||
@@ -441,10 +444,11 @@ static int brcm_usb_phy_probe(struct platform_device *pdev)
|
|||||||
priv->ini.family_id = brcmstb_get_family_id();
|
priv->ini.family_id = brcmstb_get_family_id();
|
||||||
priv->ini.product_id = brcmstb_get_product_id();
|
priv->ini.product_id = brcmstb_get_product_id();
|
||||||
|
|
||||||
match = of_match_node(brcm_usb_dt_ids, dev->of_node);
|
info = of_device_get_match_data(&pdev->dev);
|
||||||
info = match->data;
|
if (!info)
|
||||||
dvr_init = info->init_func;
|
return -ENOENT;
|
||||||
(*dvr_init)(&priv->ini);
|
|
||||||
|
info->init_func(&priv->ini);
|
||||||
|
|
||||||
dev_dbg(dev, "Best mapping table is for %s\n",
|
dev_dbg(dev, "Best mapping table is for %s\n",
|
||||||
priv->ini.family_name);
|
priv->ini.family_name);
|
||||||
|
|||||||
@@ -2298,6 +2298,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
if (total_num_lanes > MAX_NUM_LANES) {
|
if (total_num_lanes > MAX_NUM_LANES) {
|
||||||
dev_err(dev, "Invalid lane configuration\n");
|
dev_err(dev, "Invalid lane configuration\n");
|
||||||
|
ret = -EINVAL;
|
||||||
goto put_lnk_rst;
|
goto put_lnk_rst;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -82,18 +82,7 @@
|
|||||||
#define USBPCR1_PORT_RST BIT(21)
|
#define USBPCR1_PORT_RST BIT(21)
|
||||||
#define USBPCR1_WORD_IF_16BIT BIT(19)
|
#define USBPCR1_WORD_IF_16BIT BIT(19)
|
||||||
|
|
||||||
enum ingenic_usb_phy_version {
|
|
||||||
ID_JZ4770,
|
|
||||||
ID_JZ4775,
|
|
||||||
ID_JZ4780,
|
|
||||||
ID_X1000,
|
|
||||||
ID_X1830,
|
|
||||||
ID_X2000,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ingenic_soc_info {
|
struct ingenic_soc_info {
|
||||||
enum ingenic_usb_phy_version version;
|
|
||||||
|
|
||||||
void (*usb_phy_init)(struct phy *phy);
|
void (*usb_phy_init)(struct phy *phy);
|
||||||
};
|
};
|
||||||
|
|
||||||
@@ -300,38 +289,26 @@ static void x2000_usb_phy_init(struct phy *phy)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static const struct ingenic_soc_info jz4770_soc_info = {
|
static const struct ingenic_soc_info jz4770_soc_info = {
|
||||||
.version = ID_JZ4770,
|
|
||||||
|
|
||||||
.usb_phy_init = jz4770_usb_phy_init,
|
.usb_phy_init = jz4770_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ingenic_soc_info jz4775_soc_info = {
|
static const struct ingenic_soc_info jz4775_soc_info = {
|
||||||
.version = ID_JZ4775,
|
|
||||||
|
|
||||||
.usb_phy_init = jz4775_usb_phy_init,
|
.usb_phy_init = jz4775_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ingenic_soc_info jz4780_soc_info = {
|
static const struct ingenic_soc_info jz4780_soc_info = {
|
||||||
.version = ID_JZ4780,
|
|
||||||
|
|
||||||
.usb_phy_init = jz4780_usb_phy_init,
|
.usb_phy_init = jz4780_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ingenic_soc_info x1000_soc_info = {
|
static const struct ingenic_soc_info x1000_soc_info = {
|
||||||
.version = ID_X1000,
|
|
||||||
|
|
||||||
.usb_phy_init = x1000_usb_phy_init,
|
.usb_phy_init = x1000_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ingenic_soc_info x1830_soc_info = {
|
static const struct ingenic_soc_info x1830_soc_info = {
|
||||||
.version = ID_X1830,
|
|
||||||
|
|
||||||
.usb_phy_init = x1830_usb_phy_init,
|
.usb_phy_init = x1830_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ingenic_soc_info x2000_soc_info = {
|
static const struct ingenic_soc_info x2000_soc_info = {
|
||||||
.version = ID_X2000,
|
|
||||||
|
|
||||||
.usb_phy_init = x2000_usb_phy_init,
|
.usb_phy_init = x2000_usb_phy_init,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@@ -234,7 +234,7 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
|
|||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
|
|
||||||
struct platform_driver mtk_mipi_tx_driver = {
|
static struct platform_driver mtk_mipi_tx_driver = {
|
||||||
.probe = mtk_mipi_tx_probe,
|
.probe = mtk_mipi_tx_probe,
|
||||||
.remove = mtk_mipi_tx_remove,
|
.remove = mtk_mipi_tx_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
|
|||||||
@@ -143,7 +143,7 @@ static bool cpcap_usb_vbus_valid(struct cpcap_phy_ddata *ddata)
|
|||||||
|
|
||||||
error = iio_read_channel_processed(ddata->vbus, &value);
|
error = iio_read_channel_processed(ddata->vbus, &value);
|
||||||
if (error >= 0)
|
if (error >= 0)
|
||||||
return value > 3900 ? true : false;
|
return value > 3900;
|
||||||
|
|
||||||
dev_err(ddata->dev, "error reading VBUS: %i\n", error);
|
dev_err(ddata->dev, "error reading VBUS: %i\n", error);
|
||||||
|
|
||||||
|
|||||||
@@ -212,6 +212,15 @@ static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
|
|||||||
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
|
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
|
||||||
|
[QPHY_SW_RESET] = 0x00,
|
||||||
|
[QPHY_START_CTRL] = 0x44,
|
||||||
|
[QPHY_PCS_STATUS] = 0x14,
|
||||||
|
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
|
||||||
|
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
|
||||||
|
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
|
||||||
|
};
|
||||||
|
|
||||||
static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
|
static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
|
||||||
[QPHY_START_CTRL] = 0x00,
|
[QPHY_START_CTRL] = 0x00,
|
||||||
[QPHY_PCS_READY_STATUS] = 0x160,
|
[QPHY_PCS_READY_STATUS] = 0x160,
|
||||||
@@ -1974,6 +1983,291 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
|
|||||||
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
|
||||||
|
|
||||||
|
/* Rate B */
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
|
||||||
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
|
||||||
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
|
||||||
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
|
||||||
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
|
||||||
|
};
|
||||||
|
|
||||||
/* struct qmp_phy_cfg - per-PHY initialization config */
|
/* struct qmp_phy_cfg - per-PHY initialization config */
|
||||||
struct qmp_phy_cfg {
|
struct qmp_phy_cfg {
|
||||||
/* phy-type - PCIE/UFS/USB */
|
/* phy-type - PCIE/UFS/USB */
|
||||||
@@ -2183,6 +2477,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = {
|
|||||||
"ref", "ref_aux",
|
"ref", "ref_aux",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* usb3 phy on sdx55 doesn't have com_aux clock */
|
||||||
|
static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
|
||||||
|
"aux", "cfg_ahb", "ref"
|
||||||
|
};
|
||||||
|
|
||||||
/* list of resets */
|
/* list of resets */
|
||||||
static const char * const msm8996_pciephy_reset_l[] = {
|
static const char * const msm8996_pciephy_reset_l[] = {
|
||||||
"phy", "common", "cfg",
|
"phy", "common", "cfg",
|
||||||
@@ -2824,6 +3123,117 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
|
|||||||
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
|
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
|
||||||
|
.type = PHY_TYPE_USB3,
|
||||||
|
.nlanes = 1,
|
||||||
|
|
||||||
|
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
|
||||||
|
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
|
||||||
|
.tx_tbl = sdx55_usb3_uniphy_tx_tbl,
|
||||||
|
.tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
|
||||||
|
.rx_tbl = sdx55_usb3_uniphy_rx_tbl,
|
||||||
|
.rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
|
||||||
|
.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
|
||||||
|
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
|
||||||
|
.clk_list = qmp_v4_sdx55_usbphy_clk_l,
|
||||||
|
.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
|
||||||
|
.reset_list = msm8996_usb3phy_reset_l,
|
||||||
|
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
|
||||||
|
.vreg_list = qmp_phy_vreg_l,
|
||||||
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
||||||
|
.regs = qmp_v4_usb3_uniphy_regs_layout,
|
||||||
|
|
||||||
|
.start_ctrl = SERDES_START | PCS_START,
|
||||||
|
.pwrdn_ctrl = SW_PWRDN,
|
||||||
|
|
||||||
|
.has_pwrdn_delay = true,
|
||||||
|
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
|
||||||
|
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
|
||||||
|
.type = PHY_TYPE_UFS,
|
||||||
|
.nlanes = 2,
|
||||||
|
|
||||||
|
.serdes_tbl = sm8350_ufsphy_serdes_tbl,
|
||||||
|
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
|
||||||
|
.tx_tbl = sm8350_ufsphy_tx_tbl,
|
||||||
|
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
|
||||||
|
.rx_tbl = sm8350_ufsphy_rx_tbl,
|
||||||
|
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
|
||||||
|
.pcs_tbl = sm8350_ufsphy_pcs_tbl,
|
||||||
|
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
|
||||||
|
.clk_list = sdm845_ufs_phy_clk_l,
|
||||||
|
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
|
||||||
|
.vreg_list = qmp_phy_vreg_l,
|
||||||
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
||||||
|
.regs = sm8150_ufsphy_regs_layout,
|
||||||
|
|
||||||
|
.start_ctrl = SERDES_START,
|
||||||
|
.pwrdn_ctrl = SW_PWRDN,
|
||||||
|
|
||||||
|
.is_dual_lane_phy = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
|
||||||
|
.type = PHY_TYPE_USB3,
|
||||||
|
.nlanes = 1,
|
||||||
|
|
||||||
|
.serdes_tbl = sm8150_usb3_serdes_tbl,
|
||||||
|
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
|
||||||
|
.tx_tbl = sm8350_usb3_tx_tbl,
|
||||||
|
.tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
|
||||||
|
.rx_tbl = sm8350_usb3_rx_tbl,
|
||||||
|
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
|
||||||
|
.pcs_tbl = sm8350_usb3_pcs_tbl,
|
||||||
|
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
|
||||||
|
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
|
||||||
|
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
|
||||||
|
.reset_list = msm8996_usb3phy_reset_l,
|
||||||
|
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
|
||||||
|
.vreg_list = qmp_phy_vreg_l,
|
||||||
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
||||||
|
.regs = qmp_v4_usb3phy_regs_layout,
|
||||||
|
|
||||||
|
.start_ctrl = SERDES_START | PCS_START,
|
||||||
|
.pwrdn_ctrl = SW_PWRDN,
|
||||||
|
|
||||||
|
.has_pwrdn_delay = true,
|
||||||
|
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
|
||||||
|
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
|
||||||
|
|
||||||
|
.has_phy_dp_com_ctrl = true,
|
||||||
|
.is_dual_lane_phy = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
|
||||||
|
.type = PHY_TYPE_USB3,
|
||||||
|
.nlanes = 1,
|
||||||
|
|
||||||
|
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
|
||||||
|
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
|
||||||
|
.tx_tbl = sm8350_usb3_uniphy_tx_tbl,
|
||||||
|
.tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
|
||||||
|
.rx_tbl = sm8350_usb3_uniphy_rx_tbl,
|
||||||
|
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
|
||||||
|
.pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
|
||||||
|
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
|
||||||
|
.clk_list = qmp_v4_phy_clk_l,
|
||||||
|
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
|
||||||
|
.reset_list = msm8996_usb3phy_reset_l,
|
||||||
|
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
|
||||||
|
.vreg_list = qmp_phy_vreg_l,
|
||||||
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
||||||
|
.regs = sm8350_usb3_uniphy_regs_layout,
|
||||||
|
|
||||||
|
.start_ctrl = SERDES_START | PCS_START,
|
||||||
|
.pwrdn_ctrl = SW_PWRDN,
|
||||||
|
|
||||||
|
.has_pwrdn_delay = true,
|
||||||
|
.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
|
||||||
|
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
static void qcom_qmp_phy_configure_lane(void __iomem *base,
|
static void qcom_qmp_phy_configure_lane(void __iomem *base,
|
||||||
const unsigned int *regs,
|
const unsigned int *regs,
|
||||||
const struct qmp_phy_init_tbl tbl[],
|
const struct qmp_phy_init_tbl tbl[],
|
||||||
@@ -3135,7 +3545,7 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
|
|||||||
static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
|
static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
|
||||||
{
|
{
|
||||||
struct qmp_phy *qphy = phy_get_drvdata(phy);
|
struct qmp_phy *qphy = phy_get_drvdata(phy);
|
||||||
const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
|
static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
|
||||||
u8 val;
|
u8 val;
|
||||||
|
|
||||||
qphy->dp_aux_cfg++;
|
qphy->dp_aux_cfg++;
|
||||||
@@ -4128,6 +4538,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
|
|||||||
}, {
|
}, {
|
||||||
.compatible = "qcom,sc7180-qmp-usb3-dp-phy",
|
.compatible = "qcom,sc7180-qmp-usb3-dp-phy",
|
||||||
/* It's a combo phy */
|
/* It's a combo phy */
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sc8180x-qmp-ufs-phy",
|
||||||
|
.data = &sm8150_ufsphy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sc8180x-qmp-usb3-phy",
|
||||||
|
.data = &sm8150_usb3phy_cfg,
|
||||||
}, {
|
}, {
|
||||||
.compatible = "qcom,sdm845-qhp-pcie-phy",
|
.compatible = "qcom,sdm845-qhp-pcie-phy",
|
||||||
.data = &sdm845_qhp_pciephy_cfg,
|
.data = &sdm845_qhp_pciephy_cfg,
|
||||||
@@ -4170,9 +4586,21 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
|
|||||||
}, {
|
}, {
|
||||||
.compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
|
.compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
|
||||||
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sm8350-qmp-ufs-phy",
|
||||||
|
.data = &sm8350_ufsphy_cfg,
|
||||||
}, {
|
}, {
|
||||||
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
|
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
|
||||||
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sdx55-qmp-usb3-uni-phy",
|
||||||
|
.data = &sdx55_usb3_uniphy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sm8350-qmp-usb3-phy",
|
||||||
|
.data = &sm8350_usb3phy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sm8350-qmp-usb3-uni-phy",
|
||||||
|
.data = &sm8350_usb3_uniphy_cfg,
|
||||||
},
|
},
|
||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
|
|||||||
@@ -824,4 +824,151 @@
|
|||||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
|
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
|
||||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
|
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - QSERDES COM registers */
|
||||||
|
#define QSERDES_V5_COM_PLL_IVCO 0x058
|
||||||
|
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
|
||||||
|
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
|
||||||
|
#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
|
||||||
|
#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
|
||||||
|
#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
|
||||||
|
#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
|
||||||
|
#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
|
||||||
|
#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
|
||||||
|
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
|
||||||
|
#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
|
||||||
|
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
|
||||||
|
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
|
||||||
|
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
|
||||||
|
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
|
||||||
|
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
|
||||||
|
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
|
||||||
|
#define QSERDES_V5_COM_HSCLK_SEL 0x158
|
||||||
|
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
|
||||||
|
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
|
||||||
|
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
|
||||||
|
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
|
||||||
|
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
|
||||||
|
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - TX registers */
|
||||||
|
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34
|
||||||
|
#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38
|
||||||
|
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c
|
||||||
|
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40
|
||||||
|
#define QSERDES_V5_TX_LANE_MODE_1 0x84
|
||||||
|
#define QSERDES_V5_TX_LANE_MODE_2 0x88
|
||||||
|
#define QSERDES_V5_TX_LANE_MODE_3 0x8c
|
||||||
|
#define QSERDES_V5_TX_LANE_MODE_4 0x90
|
||||||
|
#define QSERDES_V5_TX_LANE_MODE_5 0x94
|
||||||
|
#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4
|
||||||
|
#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0
|
||||||
|
#define QSERDES_V5_TX_PI_QEC_CTRL 0xe4
|
||||||
|
#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
|
||||||
|
#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
|
||||||
|
#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
|
||||||
|
#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - RX registers */
|
||||||
|
#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
|
||||||
|
#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
|
||||||
|
#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||||
|
#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||||
|
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||||
|
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
|
||||||
|
#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
|
||||||
|
#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
|
||||||
|
#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
|
||||||
|
#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
|
||||||
|
#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
|
||||||
|
#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
|
||||||
|
#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
|
||||||
|
#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
|
||||||
|
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
|
||||||
|
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
|
||||||
|
#define QSERDES_V5_RX_RX_TERM_BW 0x080
|
||||||
|
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
|
||||||
|
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
|
||||||
|
#define QSERDES_V5_RX_GM_CAL 0x0dc
|
||||||
|
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
|
||||||
|
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
|
||||||
|
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
|
||||||
|
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
|
||||||
|
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||||
|
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
|
||||||
|
#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
|
||||||
|
#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
|
||||||
|
#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
|
||||||
|
#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
|
||||||
|
#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
|
||||||
|
#define QSERDES_V5_RX_SIGDET_LVL 0x120
|
||||||
|
#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||||
|
#define QSERDES_V5_RX_RX_BAND 0x128
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
|
||||||
|
#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
|
||||||
|
#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
|
||||||
|
#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
|
||||||
|
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
|
||||||
|
#define QSERDES_V5_RX_VTH_CODE 0x1b0
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - UFS PCS registers */
|
||||||
|
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
|
||||||
|
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
|
||||||
|
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
|
||||||
|
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
|
||||||
|
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
|
||||||
|
#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
|
||||||
|
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
|
||||||
|
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
|
||||||
|
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
|
||||||
|
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
|
||||||
|
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300
|
||||||
|
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
|
||||||
|
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
|
||||||
|
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
|
||||||
|
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328
|
||||||
|
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c
|
||||||
|
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330
|
||||||
|
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334
|
||||||
|
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338
|
||||||
|
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c
|
||||||
|
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340
|
||||||
|
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344
|
||||||
|
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348
|
||||||
|
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c
|
||||||
|
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350
|
||||||
|
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354
|
||||||
|
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358
|
||||||
|
#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c
|
||||||
|
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360
|
||||||
|
|
||||||
|
/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */
|
||||||
|
#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018
|
||||||
|
#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@@ -22,6 +22,7 @@
|
|||||||
|
|
||||||
#include <dt-bindings/phy/phy-qcom-qusb2.h>
|
#include <dt-bindings/phy/phy-qcom-qusb2.h>
|
||||||
|
|
||||||
|
#define QUSB2PHY_PLL 0x0
|
||||||
#define QUSB2PHY_PLL_TEST 0x04
|
#define QUSB2PHY_PLL_TEST 0x04
|
||||||
#define CLK_REF_SEL BIT(7)
|
#define CLK_REF_SEL BIT(7)
|
||||||
|
|
||||||
@@ -135,6 +136,35 @@ enum qusb2phy_reg_layout {
|
|||||||
QUSB2PHY_INTR_CTRL,
|
QUSB2PHY_INTR_CTRL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
|
||||||
|
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
|
||||||
|
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int ipq6018_regs_layout[] = {
|
||||||
|
[QUSB2PHY_PLL_STATUS] = 0x38,
|
||||||
|
[QUSB2PHY_PORT_TUNE1] = 0x80,
|
||||||
|
[QUSB2PHY_PORT_TUNE2] = 0x84,
|
||||||
|
[QUSB2PHY_PORT_TUNE3] = 0x88,
|
||||||
|
[QUSB2PHY_PORT_TUNE4] = 0x8C,
|
||||||
|
[QUSB2PHY_PORT_TUNE5] = 0x90,
|
||||||
|
[QUSB2PHY_PORT_TEST1] = 0x98,
|
||||||
|
[QUSB2PHY_PORT_TEST2] = 0x9C,
|
||||||
|
[QUSB2PHY_PORT_POWERDOWN] = 0xB4,
|
||||||
|
[QUSB2PHY_INTR_CTRL] = 0xBC,
|
||||||
|
};
|
||||||
|
|
||||||
static const unsigned int msm8996_regs_layout[] = {
|
static const unsigned int msm8996_regs_layout[] = {
|
||||||
[QUSB2PHY_PLL_STATUS] = 0x38,
|
[QUSB2PHY_PLL_STATUS] = 0x38,
|
||||||
[QUSB2PHY_PORT_TUNE1] = 0x80,
|
[QUSB2PHY_PORT_TUNE1] = 0x80,
|
||||||
@@ -245,6 +275,9 @@ struct qusb2_phy_cfg {
|
|||||||
|
|
||||||
/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
|
/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
|
||||||
bool has_pll_override;
|
bool has_pll_override;
|
||||||
|
|
||||||
|
/* true if PHY default clk scheme is single-ended */
|
||||||
|
bool se_clk_scheme_default;
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct qusb2_phy_cfg msm8996_phy_cfg = {
|
static const struct qusb2_phy_cfg msm8996_phy_cfg = {
|
||||||
@@ -253,6 +286,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
|
|||||||
.regs = msm8996_regs_layout,
|
.regs = msm8996_regs_layout,
|
||||||
|
|
||||||
.has_pll_test = true,
|
.has_pll_test = true,
|
||||||
|
.se_clk_scheme_default = true,
|
||||||
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
|
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
|
||||||
.mask_core_ready = PLL_LOCKED,
|
.mask_core_ready = PLL_LOCKED,
|
||||||
.autoresume_en = BIT(3),
|
.autoresume_en = BIT(3),
|
||||||
@@ -266,10 +300,22 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
|
|||||||
.disable_ctrl = POWER_DOWN,
|
.disable_ctrl = POWER_DOWN,
|
||||||
.mask_core_ready = CORE_READY_STATUS,
|
.mask_core_ready = CORE_READY_STATUS,
|
||||||
.has_pll_override = true,
|
.has_pll_override = true,
|
||||||
|
.se_clk_scheme_default = true,
|
||||||
.autoresume_en = BIT(0),
|
.autoresume_en = BIT(0),
|
||||||
.update_tune1_with_efuse = true,
|
.update_tune1_with_efuse = true,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
|
||||||
|
.tbl = ipq6018_init_tbl,
|
||||||
|
.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
|
||||||
|
.regs = ipq6018_regs_layout,
|
||||||
|
|
||||||
|
.disable_ctrl = POWER_DOWN,
|
||||||
|
.mask_core_ready = PLL_LOCKED,
|
||||||
|
/* autoresume not used */
|
||||||
|
.autoresume_en = BIT(0),
|
||||||
|
};
|
||||||
|
|
||||||
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
|
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
|
||||||
.tbl = qusb2_v2_init_tbl,
|
.tbl = qusb2_v2_init_tbl,
|
||||||
.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
|
.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
|
||||||
@@ -279,10 +325,23 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
|
|||||||
POWER_DOWN),
|
POWER_DOWN),
|
||||||
.mask_core_ready = CORE_READY_STATUS,
|
.mask_core_ready = CORE_READY_STATUS,
|
||||||
.has_pll_override = true,
|
.has_pll_override = true,
|
||||||
|
.se_clk_scheme_default = true,
|
||||||
.autoresume_en = BIT(0),
|
.autoresume_en = BIT(0),
|
||||||
.update_tune1_with_efuse = true,
|
.update_tune1_with_efuse = true,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct qusb2_phy_cfg sdm660_phy_cfg = {
|
||||||
|
.tbl = msm8996_init_tbl,
|
||||||
|
.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
|
||||||
|
.regs = msm8996_regs_layout,
|
||||||
|
|
||||||
|
.has_pll_test = true,
|
||||||
|
.se_clk_scheme_default = false,
|
||||||
|
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
|
||||||
|
.mask_core_ready = PLL_LOCKED,
|
||||||
|
.autoresume_en = BIT(3),
|
||||||
|
};
|
||||||
|
|
||||||
static const char * const qusb2_phy_vreg_names[] = {
|
static const char * const qusb2_phy_vreg_names[] = {
|
||||||
"vdda-pll", "vdda-phy-dpdm",
|
"vdda-pll", "vdda-phy-dpdm",
|
||||||
};
|
};
|
||||||
@@ -701,8 +760,13 @@ static int qusb2_phy_init(struct phy *phy)
|
|||||||
/* Required to get phy pll lock successfully */
|
/* Required to get phy pll lock successfully */
|
||||||
usleep_range(150, 160);
|
usleep_range(150, 160);
|
||||||
|
|
||||||
/* Default is single-ended clock on msm8996 */
|
/*
|
||||||
qphy->has_se_clk_scheme = true;
|
* Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
|
||||||
|
* register in the TCSR so, if there's none, use the default
|
||||||
|
* value hardcoded in the configuration.
|
||||||
|
*/
|
||||||
|
qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* read TCSR_PHY_CLK_SCHEME register to check if single-ended
|
* read TCSR_PHY_CLK_SCHEME register to check if single-ended
|
||||||
* clock scheme is selected. If yes, then disable differential
|
* clock scheme is selected. If yes, then disable differential
|
||||||
@@ -810,6 +874,9 @@ static const struct phy_ops qusb2_phy_gen_ops = {
|
|||||||
|
|
||||||
static const struct of_device_id qusb2_phy_of_match_table[] = {
|
static const struct of_device_id qusb2_phy_of_match_table[] = {
|
||||||
{
|
{
|
||||||
|
.compatible = "qcom,ipq6018-qusb2-phy",
|
||||||
|
.data = &ipq6018_phy_cfg,
|
||||||
|
}, {
|
||||||
.compatible = "qcom,ipq8074-qusb2-phy",
|
.compatible = "qcom,ipq8074-qusb2-phy",
|
||||||
.data = &msm8996_phy_cfg,
|
.data = &msm8996_phy_cfg,
|
||||||
}, {
|
}, {
|
||||||
@@ -818,6 +885,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
|
|||||||
}, {
|
}, {
|
||||||
.compatible = "qcom,msm8998-qusb2-phy",
|
.compatible = "qcom,msm8998-qusb2-phy",
|
||||||
.data = &msm8998_phy_cfg,
|
.data = &msm8998_phy_cfg,
|
||||||
|
}, {
|
||||||
|
.compatible = "qcom,sdm660-qusb2-phy",
|
||||||
|
.data = &sdm660_phy_cfg,
|
||||||
}, {
|
}, {
|
||||||
/*
|
/*
|
||||||
* Deprecated. Only here to support legacy device
|
* Deprecated. Only here to support legacy device
|
||||||
|
|||||||
@@ -401,13 +401,26 @@ static const struct hsphy_init_seq init_seq_femtophy[] = {
|
|||||||
HSPHY_INIT_CFG(0x90, 0x60, 0),
|
HSPHY_INIT_CFG(0x90, 0x60, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct hsphy_init_seq init_seq_mdm9607[] = {
|
||||||
|
HSPHY_INIT_CFG(0x80, 0x44, 0),
|
||||||
|
HSPHY_INIT_CFG(0x81, 0x38, 0),
|
||||||
|
HSPHY_INIT_CFG(0x82, 0x24, 0),
|
||||||
|
HSPHY_INIT_CFG(0x83, 0x13, 0),
|
||||||
|
};
|
||||||
|
|
||||||
static const struct hsphy_data hsphy_data_femtophy = {
|
static const struct hsphy_data hsphy_data_femtophy = {
|
||||||
.init_seq = init_seq_femtophy,
|
.init_seq = init_seq_femtophy,
|
||||||
.init_seq_num = ARRAY_SIZE(init_seq_femtophy),
|
.init_seq_num = ARRAY_SIZE(init_seq_femtophy),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct hsphy_data hsphy_data_mdm9607 = {
|
||||||
|
.init_seq = init_seq_mdm9607,
|
||||||
|
.init_seq_num = ARRAY_SIZE(init_seq_mdm9607),
|
||||||
|
};
|
||||||
|
|
||||||
static const struct of_device_id qcom_snps_hsphy_match[] = {
|
static const struct of_device_id qcom_snps_hsphy_match[] = {
|
||||||
{ .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, },
|
{ .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, },
|
||||||
|
{ .compatible = "qcom,usb-hs-28nm-mdm9607", .data = &hsphy_data_mdm9607, },
|
||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match);
|
MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match);
|
||||||
|
|||||||
@@ -8,7 +8,7 @@
|
|||||||
#include <linux/bitfield.h>
|
#include <linux/bitfield.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
#include <linux/io.h>
|
#include <linux/iopoll.h>
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
#include <linux/of_platform.h>
|
#include <linux/of_platform.h>
|
||||||
@@ -17,6 +17,7 @@
|
|||||||
|
|
||||||
#define STM32_USBPHYC_PLL 0x0
|
#define STM32_USBPHYC_PLL 0x0
|
||||||
#define STM32_USBPHYC_MISC 0x8
|
#define STM32_USBPHYC_MISC 0x8
|
||||||
|
#define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
|
||||||
#define STM32_USBPHYC_VERSION 0x3F4
|
#define STM32_USBPHYC_VERSION 0x3F4
|
||||||
|
|
||||||
/* STM32_USBPHYC_PLL bit fields */
|
/* STM32_USBPHYC_PLL bit fields */
|
||||||
@@ -32,19 +33,16 @@
|
|||||||
/* STM32_USBPHYC_MISC bit fields */
|
/* STM32_USBPHYC_MISC bit fields */
|
||||||
#define SWITHOST BIT(0)
|
#define SWITHOST BIT(0)
|
||||||
|
|
||||||
|
/* STM32_USBPHYC_MONITOR bit fields */
|
||||||
|
#define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
|
||||||
|
#define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
|
||||||
|
#define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
|
||||||
|
#define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
|
||||||
|
|
||||||
/* STM32_USBPHYC_VERSION bit fields */
|
/* STM32_USBPHYC_VERSION bit fields */
|
||||||
#define MINREV GENMASK(3, 0)
|
#define MINREV GENMASK(3, 0)
|
||||||
#define MAJREV GENMASK(7, 4)
|
#define MAJREV GENMASK(7, 4)
|
||||||
|
|
||||||
static const char * const supplies_names[] = {
|
|
||||||
"vdda1v1", /* 1V1 */
|
|
||||||
"vdda1v8", /* 1V8 */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define NUM_SUPPLIES ARRAY_SIZE(supplies_names)
|
|
||||||
|
|
||||||
#define PLL_LOCK_TIME_US 100
|
|
||||||
#define PLL_PWR_DOWN_TIME_US 5
|
|
||||||
#define PLL_FVCO_MHZ 2880
|
#define PLL_FVCO_MHZ 2880
|
||||||
#define PLL_INFF_MIN_RATE_HZ 19200000
|
#define PLL_INFF_MIN_RATE_HZ 19200000
|
||||||
#define PLL_INFF_MAX_RATE_HZ 38400000
|
#define PLL_INFF_MAX_RATE_HZ 38400000
|
||||||
@@ -58,7 +56,6 @@ struct pll_params {
|
|||||||
struct stm32_usbphyc_phy {
|
struct stm32_usbphyc_phy {
|
||||||
struct phy *phy;
|
struct phy *phy;
|
||||||
struct stm32_usbphyc *usbphyc;
|
struct stm32_usbphyc *usbphyc;
|
||||||
struct regulator_bulk_data supplies[NUM_SUPPLIES];
|
|
||||||
u32 index;
|
u32 index;
|
||||||
bool active;
|
bool active;
|
||||||
};
|
};
|
||||||
@@ -70,6 +67,9 @@ struct stm32_usbphyc {
|
|||||||
struct reset_control *rst;
|
struct reset_control *rst;
|
||||||
struct stm32_usbphyc_phy **phys;
|
struct stm32_usbphyc_phy **phys;
|
||||||
int nphys;
|
int nphys;
|
||||||
|
struct regulator *vdda1v1;
|
||||||
|
struct regulator *vdda1v8;
|
||||||
|
atomic_t n_pll_cons;
|
||||||
int switch_setup;
|
int switch_setup;
|
||||||
};
|
};
|
||||||
|
|
||||||
@@ -83,6 +83,41 @@ static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
|
|||||||
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
|
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = regulator_enable(usbphyc->vdda1v1);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = regulator_enable(usbphyc->vdda1v8);
|
||||||
|
if (ret)
|
||||||
|
goto vdda1v1_disable;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
vdda1v1_disable:
|
||||||
|
regulator_disable(usbphyc->vdda1v1);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = regulator_disable(usbphyc->vdda1v8);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = regulator_disable(usbphyc->vdda1v1);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
|
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
|
||||||
struct pll_params *pll_params)
|
struct pll_params *pll_params)
|
||||||
{
|
{
|
||||||
@@ -142,83 +177,106 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
|
static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
|
||||||
{
|
{
|
||||||
int i;
|
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
|
||||||
|
u32 pllen;
|
||||||
|
|
||||||
for (i = 0; i < usbphyc->nphys; i++)
|
stm32_usbphyc_clr_bits(pll_reg, PLLEN);
|
||||||
if (usbphyc->phys[i]->active)
|
|
||||||
return true;
|
|
||||||
|
|
||||||
return false;
|
/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
|
||||||
|
if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
|
||||||
|
dev_err(usbphyc->dev, "PLL not reset\n");
|
||||||
|
|
||||||
|
return stm32_usbphyc_regulators_disable(usbphyc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
|
||||||
|
{
|
||||||
|
/* Check if a phy port is still active or clk48 in use */
|
||||||
|
if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return __stm32_usbphyc_pll_disable(usbphyc);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
|
static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
|
||||||
{
|
{
|
||||||
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
|
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
|
||||||
bool pllen = (readl_relaxed(pll_reg) & PLLEN);
|
bool pllen = readl_relaxed(pll_reg) & PLLEN;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* Check if one phy port has already configured the pll */
|
/*
|
||||||
if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
|
* Check if a phy port or clk48 prepare has configured the pll
|
||||||
|
* and ensure the PLL is enabled
|
||||||
|
*/
|
||||||
|
if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (pllen) {
|
if (pllen) {
|
||||||
stm32_usbphyc_clr_bits(pll_reg, PLLEN);
|
/*
|
||||||
/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
|
* PLL shouldn't be enabled without known consumer,
|
||||||
udelay(PLL_PWR_DOWN_TIME_US);
|
* disable it and reinit n_pll_cons
|
||||||
|
*/
|
||||||
|
dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
|
||||||
|
|
||||||
|
ret = __stm32_usbphyc_pll_disable(usbphyc);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ret = stm32_usbphyc_regulators_enable(usbphyc);
|
||||||
|
if (ret)
|
||||||
|
goto dec_n_pll_cons;
|
||||||
|
|
||||||
ret = stm32_usbphyc_pll_init(usbphyc);
|
ret = stm32_usbphyc_pll_init(usbphyc);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
goto reg_disable;
|
||||||
|
|
||||||
stm32_usbphyc_set_bits(pll_reg, PLLEN);
|
stm32_usbphyc_set_bits(pll_reg, PLLEN);
|
||||||
|
|
||||||
/* Wait for maximum lock time */
|
|
||||||
udelay(PLL_LOCK_TIME_US);
|
|
||||||
|
|
||||||
if (!(readl_relaxed(pll_reg) & PLLEN)) {
|
|
||||||
dev_err(usbphyc->dev, "PLLEN not set\n");
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
|
||||||
|
|
||||||
static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
|
reg_disable:
|
||||||
{
|
stm32_usbphyc_regulators_disable(usbphyc);
|
||||||
void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
|
|
||||||
|
|
||||||
/* Check if other phy port active */
|
dec_n_pll_cons:
|
||||||
if (stm32_usbphyc_has_one_phy_active(usbphyc))
|
atomic_dec(&usbphyc->n_pll_cons);
|
||||||
return 0;
|
|
||||||
|
|
||||||
stm32_usbphyc_clr_bits(pll_reg, PLLEN);
|
return ret;
|
||||||
/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
|
|
||||||
udelay(PLL_PWR_DOWN_TIME_US);
|
|
||||||
|
|
||||||
if (readl_relaxed(pll_reg) & PLLEN) {
|
|
||||||
dev_err(usbphyc->dev, "PLL not reset\n");
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int stm32_usbphyc_phy_init(struct phy *phy)
|
static int stm32_usbphyc_phy_init(struct phy *phy)
|
||||||
{
|
{
|
||||||
struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
|
struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
|
||||||
struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
|
struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
|
||||||
|
u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
|
||||||
|
u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
|
||||||
|
STM32_USBPHYC_MON_SEL_LOCKP);
|
||||||
|
u32 monout;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = stm32_usbphyc_pll_enable(usbphyc);
|
ret = stm32_usbphyc_pll_enable(usbphyc);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
/* Check that PLL Lock input to PHY is High */
|
||||||
|
writel_relaxed(monsel, usbphyc->base + reg_mon);
|
||||||
|
ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
|
||||||
|
(monout & STM32_USBPHYC_MON_OUT_LOCKP),
|
||||||
|
100, 1000);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
|
||||||
|
(u32)(monout & STM32_USBPHYC_MON_OUT));
|
||||||
|
goto pll_disable;
|
||||||
|
}
|
||||||
|
|
||||||
usbphyc_phy->active = true;
|
usbphyc_phy->active = true;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
pll_disable:
|
||||||
|
return stm32_usbphyc_pll_disable(usbphyc);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int stm32_usbphyc_phy_exit(struct phy *phy)
|
static int stm32_usbphyc_phy_exit(struct phy *phy)
|
||||||
@@ -231,25 +289,9 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
|
|||||||
return stm32_usbphyc_pll_disable(usbphyc);
|
return stm32_usbphyc_pll_disable(usbphyc);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int stm32_usbphyc_phy_power_on(struct phy *phy)
|
|
||||||
{
|
|
||||||
struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
|
|
||||||
|
|
||||||
return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int stm32_usbphyc_phy_power_off(struct phy *phy)
|
|
||||||
{
|
|
||||||
struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
|
|
||||||
|
|
||||||
return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct phy_ops stm32_usbphyc_phy_ops = {
|
static const struct phy_ops stm32_usbphyc_phy_ops = {
|
||||||
.init = stm32_usbphyc_phy_init,
|
.init = stm32_usbphyc_phy_init,
|
||||||
.exit = stm32_usbphyc_phy_exit,
|
.exit = stm32_usbphyc_phy_exit,
|
||||||
.power_on = stm32_usbphyc_phy_power_on,
|
|
||||||
.power_off = stm32_usbphyc_phy_power_off,
|
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
};
|
};
|
||||||
|
|
||||||
@@ -312,7 +354,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
|
|||||||
struct device *dev = &pdev->dev;
|
struct device *dev = &pdev->dev;
|
||||||
struct device_node *child, *np = dev->of_node;
|
struct device_node *child, *np = dev->of_node;
|
||||||
struct phy_provider *phy_provider;
|
struct phy_provider *phy_provider;
|
||||||
u32 version;
|
u32 pllen, version;
|
||||||
int ret, port = 0;
|
int ret, port = 0;
|
||||||
|
|
||||||
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
|
usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
|
||||||
@@ -344,6 +386,19 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
|
|||||||
ret = PTR_ERR(usbphyc->rst);
|
ret = PTR_ERR(usbphyc->rst);
|
||||||
if (ret == -EPROBE_DEFER)
|
if (ret == -EPROBE_DEFER)
|
||||||
goto clk_disable;
|
goto clk_disable;
|
||||||
|
|
||||||
|
stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Wait for minimum width of powerdown pulse (ENABLE = Low):
|
||||||
|
* we have to ensure the PLL is disabled before phys initialization.
|
||||||
|
*/
|
||||||
|
if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
|
||||||
|
pllen, !(pllen & PLLEN), 5, 50)) {
|
||||||
|
dev_warn(usbphyc->dev, "PLL not reset\n");
|
||||||
|
ret = -EPROBE_DEFER;
|
||||||
|
goto clk_disable;
|
||||||
}
|
}
|
||||||
|
|
||||||
usbphyc->switch_setup = -EINVAL;
|
usbphyc->switch_setup = -EINVAL;
|
||||||
@@ -355,11 +410,26 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
|
|||||||
goto clk_disable;
|
goto clk_disable;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
|
||||||
|
if (IS_ERR(usbphyc->vdda1v1)) {
|
||||||
|
ret = PTR_ERR(usbphyc->vdda1v1);
|
||||||
|
if (ret != -EPROBE_DEFER)
|
||||||
|
dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
|
||||||
|
if (IS_ERR(usbphyc->vdda1v8)) {
|
||||||
|
ret = PTR_ERR(usbphyc->vdda1v8);
|
||||||
|
if (ret != -EPROBE_DEFER)
|
||||||
|
dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
|
||||||
|
goto clk_disable;
|
||||||
|
}
|
||||||
|
|
||||||
for_each_child_of_node(np, child) {
|
for_each_child_of_node(np, child) {
|
||||||
struct stm32_usbphyc_phy *usbphyc_phy;
|
struct stm32_usbphyc_phy *usbphyc_phy;
|
||||||
struct phy *phy;
|
struct phy *phy;
|
||||||
u32 index;
|
u32 index;
|
||||||
int i;
|
|
||||||
|
|
||||||
phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
|
phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
|
||||||
if (IS_ERR(phy)) {
|
if (IS_ERR(phy)) {
|
||||||
@@ -377,18 +447,6 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
|
|||||||
goto put_child;
|
goto put_child;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < NUM_SUPPLIES; i++)
|
|
||||||
usbphyc_phy->supplies[i].supply = supplies_names[i];
|
|
||||||
|
|
||||||
ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
|
|
||||||
usbphyc_phy->supplies);
|
|
||||||
if (ret) {
|
|
||||||
if (ret != -EPROBE_DEFER)
|
|
||||||
dev_err(&phy->dev,
|
|
||||||
"failed to get regulators: %d\n", ret);
|
|
||||||
goto put_child;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = of_property_read_u32(child, "reg", &index);
|
ret = of_property_read_u32(child, "reg", &index);
|
||||||
if (ret || index > usbphyc->nphys) {
|
if (ret || index > usbphyc->nphys) {
|
||||||
dev_err(&phy->dev, "invalid reg property: %d\n", ret);
|
dev_err(&phy->dev, "invalid reg property: %d\n", ret);
|
||||||
@@ -432,6 +490,12 @@ clk_disable:
|
|||||||
static int stm32_usbphyc_remove(struct platform_device *pdev)
|
static int stm32_usbphyc_remove(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
|
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
|
||||||
|
int port;
|
||||||
|
|
||||||
|
/* Ensure PHYs are not active, to allow PLL disabling */
|
||||||
|
for (port = 0; port < usbphyc->nphys; port++)
|
||||||
|
if (usbphyc->phys[port]->active)
|
||||||
|
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
|
||||||
|
|
||||||
clk_disable_unprepare(usbphyc->clk);
|
clk_disable_unprepare(usbphyc->clk);
|
||||||
|
|
||||||
|
|||||||
@@ -874,13 +874,10 @@ static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
|
|||||||
|
|
||||||
snprintf(name, sizeof(name), "ref%u", refclk);
|
snprintf(name, sizeof(name), "ref%u", refclk);
|
||||||
clk = devm_clk_get_optional(gtr_dev->dev, name);
|
clk = devm_clk_get_optional(gtr_dev->dev, name);
|
||||||
if (IS_ERR(clk)) {
|
if (IS_ERR(clk))
|
||||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
return dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
|
||||||
dev_err(gtr_dev->dev,
|
"Failed to get reference clock %u\n",
|
||||||
"Failed to get reference clock %u: %ld\n",
|
refclk);
|
||||||
refclk, PTR_ERR(clk));
|
|
||||||
return PTR_ERR(clk);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!clk)
|
if (!clk)
|
||||||
continue;
|
continue;
|
||||||
|
|||||||
Reference in New Issue
Block a user