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Merge tag 'amd-drm-next-6.1-2022-09-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.1-2022-09-08: amdgpu: - Mode2 reset for RDNA2 - Lots of new DC documentation - Add documentation about different asic families - DSC improvements - Aldebaran fixes - Misc spelling and grammar fixes - GFXOFF stats support for vangogh - DC frame size fixes - NBIO 7.7 updates - DCN 3.2 updates - DCN 3.1.4 Updates - SMU 13.x updates - Misc bug fixes - Rework DC register offset handling - GC 11.x updates - PSP 13.x updates - SDMA 6.x updates - GMC 11.x updates - SR-IOV updates - PSP fixes for TA unloading - DSC passthrough support - Misc code cleanups amdkfd: - ISA fixes for some GC 10.3 IPs - Misc code cleanups radeon: - Delayed work flush fix - Use time_after for some jiffies calculations drm: - DSC passthrough aux support Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908155202.57862-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
8
Documentation/gpu/amdgpu/apu-asic-info-table.csv
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8
Documentation/gpu/amdgpu/apu-asic-info-table.csv
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@@ -0,0 +1,8 @@
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Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
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Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
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Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
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Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
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Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
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SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
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Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
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Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
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|
24
Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
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24
Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
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@@ -0,0 +1,24 @@
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Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
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AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
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AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
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AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
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AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
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AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
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AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
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AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
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AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
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AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
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AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
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Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
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Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
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Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
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Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
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AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0
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MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
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MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
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AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
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AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
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AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
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AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
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AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
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AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
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|
@@ -170,7 +170,7 @@ consider asking in the amdgfx and update this page.
|
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MC
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Memory Controller
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|
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MPC
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MPC/MPCC
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Multiple pipes and plane combine
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|
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MPO
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|
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@@ -124,6 +124,65 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
|
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also apply a regamma function to introduce the gamma removed earlier back.
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Eventually, we output data in integer format at DIO.
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||||
|
||||
AMD Hardware Pipeline
|
||||
---------------------
|
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|
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When discussing graphics on Linux, the **pipeline** term can sometimes be
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||||
overloaded with multiple meanings, so it is important to define what we mean
|
||||
when we say **pipeline**. In the DCN driver, we use the term **hardware
|
||||
pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
|
||||
sequence of DCN blocks instantiated to address some specific configuration. DC
|
||||
core treats DCN blocks as individual resources, meaning we can build a pipeline
|
||||
by taking resources for all individual hardware blocks to compose one pipeline.
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||||
In actuality, we can't connect an arbitrary block from one pipe to a block from
|
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another pipe; they are routed linearly, except for DSC, which can be
|
||||
arbitrarily assigned as needed. We have this pipeline concept for trying to
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optimize bandwidth utilization.
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|
||||
.. kernel-figure:: pipeline_4k_no_split.svg
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|
||||
Additionally, let's take a look at parts of the DTN log (see
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||||
'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
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||||
this log can help us to see part of this pipeline behavior in real-time::
|
||||
|
||||
HUBP: format addr_hi width height ...
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||||
[ 0]: 8h 81h 3840 2160
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||||
[ 1]: 0h 0h 0 0
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||||
[ 2]: 0h 0h 0 0
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||||
[ 3]: 0h 0h 0 0
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[ 4]: 0h 0h 0 0
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||||
...
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||||
MPCC: OPP DPP ...
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||||
[ 0]: 0h 0h ...
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||||
|
||||
The first thing to notice from the diagram and DTN log it is the fact that we
|
||||
have different clock domains for each part of the DCN blocks. In this example,
|
||||
we have just a single **pipeline** where the data flows from DCHUB to DIO, as
|
||||
we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
|
||||
we can split this single pipe differently, as described in the below diagram:
|
||||
|
||||
.. kernel-figure:: pipeline_4k_split.svg
|
||||
|
||||
Now, if we inspect the DTN log again we can see some interesting changes::
|
||||
|
||||
HUBP: format addr_hi width height ...
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||||
[ 0]: 8h 81h 1920 2160 ...
|
||||
...
|
||||
[ 4]: 0h 0h 0 0 ...
|
||||
[ 5]: 8h 81h 1920 2160 ...
|
||||
...
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||||
MPCC: OPP DPP ...
|
||||
[ 0]: 0h 0h ...
|
||||
[ 5]: 0h 5h ...
|
||||
|
||||
From the above example, we now split the display pipeline into two vertical
|
||||
parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
|
||||
clock frequency in the DPP part. This is not only useful for saving power but
|
||||
also to better handle the required throughput. The idea to keep in mind here is
|
||||
that the pipe configuration can vary a lot according to the display
|
||||
configuration, and it is the DML's responsibility to set up all required
|
||||
configuration parameters for multiple scenarios supported by our hardware.
|
||||
|
||||
Global Sync
|
||||
-----------
|
||||
|
||||
|
||||
1370
Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
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1370
Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
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|
After Width: | Height: | Size: 56 KiB |
1529
Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
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1529
Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
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|
After Width: | Height: | Size: 63 KiB |
@@ -40,3 +40,144 @@ Atomic Implementation
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
|
||||
:functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
|
||||
|
||||
Color Management Properties
|
||||
===========================
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
|
||||
:doc: overview
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
|
||||
:internal:
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||||
|
||||
|
||||
DC Color Capabilities between DCN generations
|
||||
---------------------------------------------
|
||||
|
||||
DRM/KMS framework defines three CRTC color correction properties: degamma,
|
||||
color transformation matrix (CTM) and gamma, and two properties for degamma and
|
||||
gamma LUT sizes. AMD DC programs some of the color correction features
|
||||
pre-blending but DRM/KMS has not per-plane color correction properties.
|
||||
|
||||
In general, the DRM CRTC color properties are programmed to DC, as follows:
|
||||
CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is
|
||||
programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other
|
||||
color caps available in the hw is not currently exposed by DRM interface and
|
||||
are bypassed.
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
|
||||
:doc: color-management-caps
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
|
||||
:internal:
|
||||
|
||||
The color pipeline has undergone major changes between DCN hardware
|
||||
generations. What's possible to do before and after blending depends on
|
||||
hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families
|
||||
schemas.
|
||||
|
||||
**DCN 2.0 family color caps and mapping**
|
||||
|
||||
.. kernel-figure:: dcn2_cm_drm_current.svg
|
||||
|
||||
**DCN 3.0 family color caps and mapping**
|
||||
|
||||
.. kernel-figure:: dcn3_cm_drm_current.svg
|
||||
|
||||
Blend Mode Properties
|
||||
=====================
|
||||
|
||||
Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
|
||||
describes how pixels from a foreground plane (fg) are composited with the
|
||||
background plane (bg). Here, we present main concepts of DRM blend mode to help
|
||||
to understand how this property is mapped to AMD DC interface. See more about
|
||||
this DRM property and the alpha blending equations in :ref:`DRM Plane
|
||||
Composition Properties <plane_composition_properties>`.
|
||||
|
||||
Basically, a blend mode sets the alpha blending equation for plane
|
||||
composition that fits the mode in which the alpha channel affects the state of
|
||||
pixel color values and, therefore, the resulted pixel color. For
|
||||
example, consider the following elements of the alpha blending equation:
|
||||
|
||||
- *fg.rgb*: Each of the RGB component values from the foreground's pixel.
|
||||
- *fg.alpha*: Alpha component value from the foreground's pixel.
|
||||
- *bg.rgb*: Each of the RGB component values from the background.
|
||||
- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see
|
||||
more in :ref:`DRM Plane Composition Properties <plane_composition_properties>`.
|
||||
|
||||
in the basic alpha blending equation::
|
||||
|
||||
out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
|
||||
|
||||
the alpha channel value of each pixel in a plane is ignored and only the plane
|
||||
alpha affects the resulted pixel color values.
|
||||
|
||||
DRM has three blend mode to define the blend formula in the plane composition:
|
||||
|
||||
* **None**: Blend formula that ignores the pixel alpha.
|
||||
|
||||
* **Pre-multiplied**: Blend formula that assumes the pixel color values in a
|
||||
plane was already pre-multiplied by its own alpha channel before storage.
|
||||
|
||||
* **Coverage**: Blend formula that assumes the pixel color values were not
|
||||
pre-multiplied with the alpha channel values.
|
||||
|
||||
and pre-multiplied is the default pixel blend mode, that means, when no blend
|
||||
mode property is created or defined, DRM considers the plane's pixels has
|
||||
pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
|
||||
provides a set of subtests to verify plane alpha and blend mode properties.
|
||||
|
||||
The DRM blend mode and its elements are then mapped by AMDGPU display manager
|
||||
(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
|
||||
(MPC), as follows:
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
|
||||
:doc: mpc-overview
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
|
||||
:functions: mpcc_blnd_cfg
|
||||
|
||||
Therefore, the blending configuration for a single MPCC instance on the MPC
|
||||
tree is defined by :c:type:`mpcc_blnd_cfg`, where
|
||||
:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
|
||||
set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
|
||||
multiplied (true/false), being only true for DRM pre-multiplied blend mode.
|
||||
:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
|
||||
alpha and plane alpha values. It sets one of the three modes for
|
||||
:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
|
||||
:functions: mpcc_alpha_blend_mode
|
||||
|
||||
DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
|
||||
blend formula, as follows:
|
||||
|
||||
* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value
|
||||
from the plane's pixel
|
||||
* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should
|
||||
be ignored and, therefore, pixel values are not pre-multiplied
|
||||
* *MPC global gain* assumes *MPC global alpha* value when both *DRM
|
||||
fg.alpha* and *DRM plane_alpha* participate in the blend equation
|
||||
|
||||
In short, *fg.alpha* is ignored by selecting
|
||||
:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
|
||||
fg.alpha) component becomes available by selecting
|
||||
:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
|
||||
:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
|
||||
pre-multiplied by alpha or not.
|
||||
|
||||
Blend configuration flow
|
||||
------------------------
|
||||
|
||||
The alpha blending equation is configured from DRM to DC interface by the
|
||||
following path:
|
||||
|
||||
1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
|
||||
:c:type:`fill_blending_from_plane_state()` that maps
|
||||
:c:type:`drm_plane_state <drm_plane_state>` attributes to
|
||||
:c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
|
||||
OS-agnostic component (DC).
|
||||
|
||||
2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
|
||||
MPCC blend configuration considering the :c:type:`dc_plane_info
|
||||
<dc_plane_info>` input from DPP.
|
||||
|
||||
@@ -28,4 +28,5 @@ table of content:
|
||||
display-manager.rst
|
||||
dc-debug.rst
|
||||
dcn-overview.rst
|
||||
mpo-overview.rst
|
||||
dc-glossary.rst
|
||||
|
||||
435
Documentation/gpu/amdgpu/display/mpo-cursor.svg
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435
Documentation/gpu/amdgpu/display/mpo-cursor.svg
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@@ -0,0 +1,435 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
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|
||||
|
||||
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|
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xmlns:svg="http://www.w3.org/2000/svg"
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After Width: | Height: | Size: 18 KiB |
242
Documentation/gpu/amdgpu/display/mpo-overview.rst
Normal file
242
Documentation/gpu/amdgpu/display/mpo-overview.rst
Normal file
@@ -0,0 +1,242 @@
|
||||
========================
|
||||
Multiplane Overlay (MPO)
|
||||
========================
|
||||
|
||||
.. note:: You will get more from this page if you have already read the
|
||||
'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
|
||||
|
||||
|
||||
Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via
|
||||
fixed-function hardware in the display controller rather than using graphics or
|
||||
compute shaders for composition. This can yield some power savings if it means
|
||||
the graphics/compute pipelines can be put into low-power states. In summary,
|
||||
MPO can bring the following benefits:
|
||||
|
||||
* Decreased GPU and CPU workload - no composition shaders needed, no extra
|
||||
buffer copy needed, GPU can remain idle.
|
||||
* Plane independent page flips - No need to be tied to global compositor
|
||||
page-flip present rate, reduced latency, independent timing.
|
||||
|
||||
.. note:: Keep in mind that MPO is all about power-saving; if you want to learn
|
||||
more about power-save in the display context, check the link:
|
||||
`Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
|
||||
|
||||
Multiplane Overlay is only available using the DRM atomic model. The atomic
|
||||
model only uses a single userspace IOCTL for configuring the display hardware
|
||||
(modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware
|
||||
resources and limitations userspace also calls into drmModeGetResources which
|
||||
reports back the number of planes, CRTCs, and connectors. There are three types
|
||||
of DRM planes that the driver can register and work with:
|
||||
|
||||
* ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
|
||||
CRTC, primary planes are the planes operated upon by CRTC modesetting and
|
||||
flipping operations.
|
||||
* ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
|
||||
CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs
|
||||
* ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary,
|
||||
non-cursor planes. Some drivers refer to these types of planes as "sprites"
|
||||
internally.
|
||||
|
||||
To illustrate how it works, let's take a look at a device that exposes the
|
||||
following planes to userspace:
|
||||
|
||||
* 4 Primary planes (1 per CRTC).
|
||||
* 4 Cursor planes (1 per CRTC).
|
||||
* 1 Overlay plane (shared among CRTCs).
|
||||
|
||||
.. note:: Keep in mind that different ASICs might expose other numbers of
|
||||
planes.
|
||||
|
||||
For this hardware example, we have 4 pipes (if you don't know what AMD pipe
|
||||
means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section
|
||||
"AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split
|
||||
configuration for optimal single display output (e.g., 2 pipes per plane).
|
||||
|
||||
A typical MPO configuration from userspace - 1 primary + 1 overlay on a single
|
||||
display - will see 4 pipes in use, 2 per plane.
|
||||
|
||||
At least 1 pipe must be used per plane (primary and overlay), so for this
|
||||
hypothetical hardware that we are using as an example, we have an absolute
|
||||
limit of 4 planes across all CRTCs. Atomic commits will be rejected for display
|
||||
configurations using more than 4 planes. Again, it is important to stress that
|
||||
every DCN has different restrictions; here, we are just trying to provide the
|
||||
concept idea.
|
||||
|
||||
Plane Restrictions
|
||||
==================
|
||||
|
||||
AMDGPU imposes restrictions on the use of DRM planes in the driver.
|
||||
|
||||
Atomic commits will be rejected for commits which do not follow these
|
||||
restrictions:
|
||||
|
||||
* Overlay planes must be in ARGB8888 or XRGB8888 format
|
||||
* Planes cannot be placed outside of the CRTC destination rectangle
|
||||
* Planes cannot be downscaled more than 1/4x of their original size
|
||||
* Planes cannot be upscaled more than 16x of their original size
|
||||
|
||||
Not every property is available on every plane:
|
||||
|
||||
* Only primary planes have color-space and non-RGB format support
|
||||
* Only overlay planes have alpha blending support
|
||||
|
||||
Cursor Restrictions
|
||||
===================
|
||||
|
||||
Before we start to describe some restrictions around cursor and MPO, see the
|
||||
below image:
|
||||
|
||||
.. kernel-figure:: mpo-cursor.svg
|
||||
|
||||
The image on the left side represents how DRM expects the cursor and planes to
|
||||
be blended. However, AMD hardware handles cursors differently, as you can see
|
||||
on the right side; basically, our cursor cannot be drawn outside its associated
|
||||
plane as it is being treated as part of the plane. Another consequence of that
|
||||
is that cursors inherit the color and scale from the plane.
|
||||
|
||||
As a result of the above behavior, do not use legacy API to set up the cursor
|
||||
plane when working with MPO; otherwise, you might encounter unexpected
|
||||
behavior.
|
||||
|
||||
In short, AMD HW has no dedicated cursor planes. A cursor is attached to
|
||||
another plane and therefore inherits any scaling or color processing from its
|
||||
parent plane.
|
||||
|
||||
Use Cases
|
||||
=========
|
||||
|
||||
Picture-in-Picture (PIP) playback - Underlay strategy
|
||||
-----------------------------------------------------
|
||||
|
||||
Video playback should be done using the "primary plane as underlay" MPO
|
||||
strategy. This is a 2 planes configuration:
|
||||
|
||||
* 1 YUV DRM Primary Plane (e.g. NV12 Video)
|
||||
* 1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should
|
||||
prepare the framebuffers for the planes as follows:
|
||||
- The overlay plane contains general desktop UI, video player controls, and video subtitles
|
||||
- Primary plane contains one or more videos
|
||||
|
||||
.. note:: Keep in mind that we could extend this configuration to more planes,
|
||||
but that is currently not supported by our driver yet (maybe if we have a
|
||||
userspace request in the future, we can change that).
|
||||
|
||||
See below a single-video example:
|
||||
|
||||
.. kernel-figure:: single-display-mpo.svg
|
||||
|
||||
.. note:: We could extend this behavior to more planes, but that is currently
|
||||
not supported by our driver.
|
||||
|
||||
The video buffer should be used directly for the primary plane. The video can
|
||||
be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y,
|
||||
CRTC_W, and CRTC_H. The primary plane should also have the color encoding and
|
||||
color range properties set based on the source content:
|
||||
|
||||
* ``COLOR_RANGE``, ``COLOR_ENCODING``
|
||||
|
||||
The overlay plane should be the native size of the CRTC. The compositor must
|
||||
draw a transparent cutout for where the video should be placed on the desktop
|
||||
(i.e., set the alpha to zero). The primary plane video will be visible through
|
||||
the underlay. The overlay plane's buffer may remain static while the primary
|
||||
plane's framebuffer is used for standard double-buffered playback.
|
||||
|
||||
The compositor should create a YUV buffer matching the native size of the CRTC.
|
||||
Each video buffer should be composited onto this YUV buffer for direct YUV
|
||||
scanout. The primary plane should have the color encoding and color range
|
||||
properties set based on the source content: ``COLOR_RANGE``,
|
||||
``COLOR_ENCODING``. However, be mindful that the source color space and
|
||||
encoding match for each video since it affect the entire plane.
|
||||
|
||||
The overlay plane should be the native size of the CRTC. The compositor must
|
||||
draw a transparent cutout for where each video should be placed on the desktop
|
||||
(i.e., set the alpha to zero). The primary plane videos will be visible through
|
||||
the underlay. The overlay plane's buffer may remain static while compositing
|
||||
operations for video playback will be done on the video buffer.
|
||||
|
||||
This kernel interface is validated using IGT GPU Tools. The following tests can
|
||||
be run to validate positioning, blending, scaling under a variety of sequences
|
||||
and interactions with operations such as DPMS and S3:
|
||||
|
||||
- ``kms_plane@plane-panning-bottom-right-pipe-*-planes``
|
||||
- ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``
|
||||
- ``kms_plane@plane-panning-top-left-pipe-*-``
|
||||
- ``kms_plane@plane-position-covered-pipe-*-``
|
||||
- ``kms_plane@plane-position-hole-dpms-pipe-*-``
|
||||
- ``kms_plane@plane-position-hole-pipe-*-``
|
||||
- ``kms_plane_multiple@atomic-pipe-*-tiling-``
|
||||
- ``kms_plane_scaling@pipe-*-plane-scaling``
|
||||
- ``kms_plane_alpha_blend@pipe-*-alpha-basic``
|
||||
- ``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb``
|
||||
- ``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb``
|
||||
- ``kms_plane_alpha_blend@pipe-*-constant-alpha-min``
|
||||
- ``kms_plane_alpha_blend@pipe-*-constant-alpha-mid``
|
||||
- ``kms_plane_alpha_blend@pipe-*-constant-alpha-max``
|
||||
|
||||
Multiple Display MPO
|
||||
--------------------
|
||||
|
||||
AMDGPU supports display MPO when using multiple displays; however, this feature
|
||||
behavior heavily relies on the compositor implementation. Keep in mind that
|
||||
usespace can define different policies. For example, some OSes can use MPO to
|
||||
protect the plane that handles the video playback; notice that we don't have
|
||||
many limitations for a single display. Nonetheless, this manipulation can have
|
||||
many more restrictions for a multi-display scenario. The below example shows a
|
||||
video playback in the middle of two displays, and it is up to the compositor to
|
||||
define a policy on how to handle it:
|
||||
|
||||
.. kernel-figure:: multi-display-hdcp-mpo.svg
|
||||
|
||||
Let's discuss some of the hardware limitations we have when dealing with
|
||||
multi-display with MPO.
|
||||
|
||||
Limitations
|
||||
~~~~~~~~~~~
|
||||
|
||||
For simplicity's sake, for discussing the hardware limitation, this
|
||||
documentation supposes an example where we have two displays and video playback
|
||||
that will be moved around different displays.
|
||||
|
||||
* **Hardware limitations**
|
||||
|
||||
From the DCN overview page, each display requires at least one pipe and each
|
||||
MPO plane needs another pipe. As a result, when the video is in the middle of
|
||||
the two displays, we need to use 2 pipes. See the example below where we avoid
|
||||
pipe split:
|
||||
|
||||
- 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
|
||||
- 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
|
||||
middle of both displays needs 2 pipes.
|
||||
- 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
|
||||
|
||||
If we use MPO with multiple displays, the userspace has to decide to enable
|
||||
multiple MPO by the price of limiting the number of external displays supported
|
||||
or disable it in favor of multiple displays; it is a policy decision. For
|
||||
example:
|
||||
|
||||
* When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
|
||||
* When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
|
||||
|
||||
Let's briefly explore how userspace can handle these two display configurations
|
||||
on an ASIC that only supports three pipes. We can have:
|
||||
|
||||
.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg
|
||||
|
||||
- Total pipes are 3
|
||||
- User lights up 2 displays (2 out of 3 pipes are used)
|
||||
- User launches video (1 pipe used for MPO)
|
||||
- Now, if the user moves the video in the middle of 2 displays, one part of the
|
||||
video won't be MPO since we have used 3/3 pipes.
|
||||
|
||||
* **Scaling limitation**
|
||||
|
||||
MPO cannot handle scaling less than 0.25 and more than x16. For example:
|
||||
|
||||
If 4k video (3840x2160) is playing in windowed mode, the physical size of the
|
||||
window cannot be smaller than (960x540).
|
||||
|
||||
.. note:: These scaling limitations might vary from ASIC to ASIC.
|
||||
|
||||
* **Size Limitation**
|
||||
|
||||
The minimum MPO size is 12px.
|
||||
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After Width: | Height: | Size: 11 KiB |
@@ -32,6 +32,23 @@ unique_id
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.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
|
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:doc: unique_id
|
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|
||||
Accelerated Processing Units (APU) Info
|
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---------------------------------------
|
||||
|
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.. csv-table::
|
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:header-rows: 1
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:widths: 3, 2, 2, 1, 1, 1
|
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:file: ./apu-asic-info-table.csv
|
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Discrete GPU Info
|
||||
-----------------
|
||||
|
||||
.. csv-table::
|
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:header-rows: 1
|
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:widths: 3, 2, 2, 1, 1, 1
|
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:file: ./dgpu-asic-info-table.csv
|
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|
||||
|
||||
GPU Memory Usage Information
|
||||
============================
|
||||
|
||||
|
||||
@@ -72,7 +72,8 @@ card's RLC (RunList Controller) firmware powers off the gfx engine
|
||||
dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by
|
||||
default on supported GPUs.
|
||||
|
||||
Userspace can interact with GFXOFF through a debugfs interface:
|
||||
Userspace can interact with GFXOFF through a debugfs interface (all values in
|
||||
`uint32_t`, unless otherwise noted):
|
||||
|
||||
``amdgpu_gfxoff``
|
||||
-----------------
|
||||
@@ -104,3 +105,18 @@ Read it to check current GFXOFF's status of a GPU::
|
||||
If GFXOFF is enabled, the value will be transitioning around [0, 3], always
|
||||
getting into 0 when possible. When it's disabled, it's always at 2. Returns
|
||||
``-EINVAL`` if it's not supported.
|
||||
|
||||
``amdgpu_gfxoff_count``
|
||||
-----------------------
|
||||
|
||||
Read it to get the total GFXOFF entry count at the time of query since system
|
||||
power-up. The value is an `uint64_t` type, however, due to firmware limitations,
|
||||
it can currently overflow as an `uint32_t`. *Only supported in vangogh*
|
||||
|
||||
``amdgpu_gfxoff_residency``
|
||||
---------------------------
|
||||
|
||||
Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to
|
||||
get average GFXOFF residency % multiplied by 100 during the last logging
|
||||
interval. E.g. a value of 7854 means 78.54% of the time in the last logging
|
||||
interval the GPU was in GFXOFF mode. *Only supported in vangogh*
|
||||
|
||||
@@ -532,6 +532,8 @@ Standard Plane Properties
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_plane.c
|
||||
:doc: standard plane properties
|
||||
|
||||
.. _plane_composition_properties:
|
||||
|
||||
Plane Composition Properties
|
||||
----------------------------
|
||||
|
||||
|
||||
Reference in New Issue
Block a user