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clk: gcc-sm8150: drop PLL test clock

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There is no user of core_bi_pll_test_se test clock so drop it.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228140917.118861-2-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
2022-12-28 15:09:16 +01:00
committed by Bjorn Andersson
parent 3db8732c55
commit 412df0f95a
1 changed files with 0 additions and 17 deletions
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17
drivers/clk/qcom/gcc-sm8150.c
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@@ -26,7 +26,6 @@
enum { enum {
P_BI_TCXO, P_BI_TCXO,
P_AUD_REF_CLK, P_AUD_REF_CLK,
P_CORE_BI_PLL_TEST_SE,
P_GPLL0_OUT_EVEN, P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN,
P_GPLL7_OUT_MAIN, P_GPLL7_OUT_MAIN,
@@ -117,14 +116,12 @@ static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 }, { P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 }, { P_GPLL0_OUT_EVEN, 6 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_0[] = { static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_1[] = { static const struct parent_map gcc_parent_map_1[] = {
@@ -132,7 +129,6 @@ static const struct parent_map gcc_parent_map_1[] = {
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 }, { P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 }, { P_GPLL0_OUT_EVEN, 6 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_1[] = { static const struct clk_parent_data gcc_parents_1[] = {
@@ -140,41 +136,34 @@ static const struct clk_parent_data gcc_parents_1[] = {
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" }, { .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_2[] = { static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 }, { P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 }, { P_SLEEP_CLK, 5 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_2[] = { static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" }, { .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_3[] = { static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 }, { P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_3[] = { static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .fw_name = "core_bi_pll_test_se"},
}; };
static const struct parent_map gcc_parent_map_4[] = { static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 }, { P_BI_TCXO, 0 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_4[] = { static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_5[] = { static const struct parent_map gcc_parent_map_5[] = {
@@ -182,7 +171,6 @@ static const struct parent_map gcc_parent_map_5[] = {
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL7_OUT_MAIN, 3 }, { P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL0_OUT_EVEN, 6 }, { P_GPLL0_OUT_EVEN, 6 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_5[] = { static const struct clk_parent_data gcc_parents_5[] = {
@@ -190,7 +178,6 @@ static const struct clk_parent_data gcc_parents_5[] = {
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .hw = &gpll7.clkr.hw }, { .hw = &gpll7.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_6[] = { static const struct parent_map gcc_parent_map_6[] = {
@@ -198,7 +185,6 @@ static const struct parent_map gcc_parent_map_6[] = {
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_MAIN, 2 }, { P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 }, { P_GPLL0_OUT_EVEN, 6 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_6[] = { static const struct clk_parent_data gcc_parents_6[] = {
@@ -206,7 +192,6 @@ static const struct clk_parent_data gcc_parents_6[] = {
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw }, { .hw = &gpll9.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct parent_map gcc_parent_map_7[] = { static const struct parent_map gcc_parent_map_7[] = {
@@ -214,7 +199,6 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 }, { P_AUD_REF_CLK, 2 },
{ P_GPLL0_OUT_EVEN, 6 }, { P_GPLL0_OUT_EVEN, 6 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const struct clk_parent_data gcc_parents_7[] = { static const struct clk_parent_data gcc_parents_7[] = {
@@ -222,7 +206,6 @@ static const struct clk_parent_data gcc_parents_7[] = {
{ .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw },
{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
{ .hw = &gpll0_out_even.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se" },
}; };
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {