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pwm: lpss: Allow other drivers to enable PWM LPSS

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The PWM LPSS device can be embedded in another device.
In order to enable it, allow that drivers to probe
a corresponding device.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Andy Shevchenko
2022-11-17 13:08:03 +02:00
parent 878cf979c1
commit 2fd36aa0ad
2 changed files with 34 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/pwm/pwm-lpss.h
View File

@@ -13,7 +13,7 @@
#include <linux/pwm.h> #include <linux/pwm.h>
#include <linux/types.h> #include <linux/types.h>
struct device; #include <linux/platform_data/x86/pwm-lpss.h>
#define LPSS_MAX_PWMS 4 #define LPSS_MAX_PWMS 4
@@ -23,29 +23,9 @@ struct pwm_lpss_chip {
const struct pwm_lpss_boardinfo *info; const struct pwm_lpss_boardinfo *info;
}; };
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
/*
* Some versions of the IP may stuck in the state machine if enable
* bit is not set, and hence update bit will show busy status till
* the reset. For the rest it may be otherwise.
*/
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
* messes with the PWM0 controllers state,
*/
bool other_devices_aml_touches_pwm_regs;
};
extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info; extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info);
#endif /* __PWM_LPSS_H */ #endif /* __PWM_LPSS_H */

33
include/linux/platform_data/x86/pwm-lpss.h Normal file
View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Intel Low Power Subsystem PWM controller driver */
#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
#define __PLATFORM_DATA_X86_PWM_LPSS_H
#include <linux/types.h>
struct device;
struct pwm_lpss_chip;
struct pwm_lpss_boardinfo {
unsigned long clk_rate;
unsigned int npwm;
unsigned long base_unit_bits;
/*
* Some versions of the IP may stuck in the state machine if enable
* bit is not set, and hence update bit will show busy status till
* the reset. For the rest it may be otherwise.
*/
bool bypass;
/*
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
* messes with the PWM0 controllers state,
*/
bool other_devices_aml_touches_pwm_regs;
};
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
const struct pwm_lpss_boardinfo *info);
#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */