mirror of
https://github.com/Ralim/IronOS.git
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280 lines
8.9 KiB
C++
280 lines
8.9 KiB
C++
/*
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* FRToSI2C.cpp
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*
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* Created on: 14Apr.,2018
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* Author: Ralim
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*/
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#include "BSP.h"
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#include "IRQ.h"
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#include "Setup.h"
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#include "bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h"
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extern "C" {
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#include "bflb_platform.h"
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#include "bl702_dma.h"
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#include "bl702_glb.h"
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#include "bl702_i2c.h"
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}
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#include <I2C_Wrapper.hpp>
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// Semaphore for locking users of I2C
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SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
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StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
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#define I2C_TIME_OUT (uint16_t)(12000)
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#define I2C_NOTIFY_INDEX 1
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#define I2C_TX_FIFO_ADDR (0x4000A300 + 0x88)
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#define I2C_RX_FIFO_ADDR (0x4000A300 + 0x8C)
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// Used by the irq handler
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volatile uint8_t *IRQDataPointer;
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volatile uint8_t IRQDataSizeLeft;
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volatile bool IRQFailureMarker;
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volatile TaskHandle_t IRQTaskWaitingHandle = NULL;
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/****** IRQ Handlers ******/
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void i2c_irq_tx_fifo_low() {
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// Filling tx fifo
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// Fifo is 32 bit, LSB sent first
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// FiFo can store up to 2, 32-bit words
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// So we fill it until it has no free room (or we run out of data)
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while (IRQDataSizeLeft > 0 && I2C_GetTXFIFOAvailable() > 0) {
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// Can put in at least 1 byte
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// Build a 32-bit word from bytes
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uint32_t value = 0;
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int packing = IRQDataSizeLeft >= 4 ? 0 : 4 - IRQDataSizeLeft;
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for (int i = 0; i < 4 && IRQDataSizeLeft > 0; i++) {
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value >>= 8;
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value |= (*IRQDataPointer) << 24; // Shift to the left, adding new data to the higher byte
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IRQDataPointer++; // Shift to next byte
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IRQDataSizeLeft--;
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}
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// Handle shunting remaining bytes if not a full 4 to send
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for (int i = 0; i < packing; i++) {
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value >>= 8;
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}
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// Push the new value to the fifo
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*((volatile uint32_t *)I2C_TX_FIFO_ADDR) = value;
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}
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if (IRQDataSizeLeft == 0) {
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// Disable IRQ, were done
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I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, MASK);
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}
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}
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void i2c_rx_pop_fifo() {
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// Pop one word from the fifo and store it
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uint32_t value = *((uint32_t *)I2C_RX_FIFO_ADDR);
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for (int i = 0; i < 4 && IRQDataSizeLeft > 0; i++) {
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*IRQDataPointer = value & 0xFF;
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IRQDataPointer++;
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IRQDataSizeLeft--;
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value >>= 8;
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}
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}
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void i2c_irq_rx_fifo_ready() {
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// Draining the Rx FiFo
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while (I2C_GetRXFIFOAvailable() > 0) {
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i2c_rx_pop_fifo();
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}
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if (IRQDataSizeLeft == 0) {
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// Disable IRQ, were done
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I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, MASK);
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}
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}
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void i2c_irq_done_read() {
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IRQFailureMarker = false;
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// If there was a non multiple of 4 bytes to be read, they are pushed to the fifo now (end of transfer interrupt)
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// So we catch them here
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while (I2C_GetRXFIFOAvailable() > 0) {
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i2c_rx_pop_fifo();
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}
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// Mask IRQ's back off
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FRToSI2C::CpltCallback(); // Causes the lock to be released
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}
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void i2c_irq_done() {
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IRQFailureMarker = false;
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// Mask IRQ's back off
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FRToSI2C::CpltCallback(); // Causes the lock to be released
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}
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void i2c_irq_nack() {
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IRQFailureMarker = true;
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// Mask IRQ's back off
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FRToSI2C::CpltCallback(); // Causes the lock to be released
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}
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/****** END IRQ Handlers ******/
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void FRToSI2C::CpltCallback() {
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// This is only triggered from IRQ context
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I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, MASK);
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I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, MASK);
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I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, MASK);
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I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, MASK);
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CPU_Interrupt_Disable(I2C_IRQn); // Disable IRQ's
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I2C_Disable(I2C0_ID); // Disable I2C to tidy up
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// Unlock the semaphore && allow task switch if desired by RTOS
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BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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xSemaphoreGiveFromISR(I2CSemaphore, &xHigherPriorityTaskWoken);
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xTaskNotifyIndexedFromISR(IRQTaskWaitingHandle, I2C_NOTIFY_INDEX, IRQFailureMarker ? 2 : 1, eSetValueWithOverwrite, &xHigherPriorityTaskWoken);
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portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
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}
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bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
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uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
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uint8_t temp = 0;
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Mem_Read(add, reg, &temp, 1);
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return temp;
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}
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bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) {
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if (!lock()) {
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return false;
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}
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I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0};
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BL_Err_Type err = ERROR;
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i2cCfg.slaveAddr = DevAddress >> 1;
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i2cCfg.stopEveryByte = DISABLE;
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i2cCfg.subAddr = read_address;
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i2cCfg.dataSize = number_of_byte;
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i2cCfg.data = p_buffer;
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i2cCfg.subAddrSize = 1; // one byte address
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// Store handles for IRQ
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IRQDataPointer = p_buffer;
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IRQDataSizeLeft = number_of_byte;
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IRQTaskWaitingHandle = xTaskGetCurrentTaskHandle();
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IRQFailureMarker = false;
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I2C_Disable(I2C0_ID);
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// Setup and run
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I2C_Init(I2C0_ID, I2C_READ, &i2cCfg); // Setup hardware for the I2C init header with the device address
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I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK);
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I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK);
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I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, UNMASK);
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I2C_Int_Callback_Install(I2C0_ID, I2C_TRANS_END_INT, i2c_irq_done_read);
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I2C_Int_Callback_Install(I2C0_ID, I2C_NACK_RECV_INT, i2c_irq_nack);
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I2C_Int_Callback_Install(I2C0_ID, I2C_RX_FIFO_READY_INT, i2c_irq_rx_fifo_ready);
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CPU_Interrupt_Enable(I2C_IRQn);
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CPU_Interrupt_Disable(BLE_IRQn);
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// Start
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I2C_Enable(I2C0_ID);
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// Wait for transfer in background
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uint32_t result = 0;
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xTaskNotifyWaitIndexed(I2C_NOTIFY_INDEX, 0xFFFFFFFF, 0xFFFFFFFF, &result, 0xFFFFFFFF);
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CPU_Interrupt_Enable(BLE_IRQn);
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return result == 1;
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}
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bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) {
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if (!lock()) {
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return false;
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}
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I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0};
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BL_Err_Type err = ERROR;
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i2cCfg.slaveAddr = DevAddress >> 1;
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i2cCfg.stopEveryByte = DISABLE;
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i2cCfg.subAddr = MemAddress;
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i2cCfg.dataSize = number_of_byte;
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i2cCfg.data = p_buffer;
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i2cCfg.subAddrSize = 1; // one byte address
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// Store handles for IRQ
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IRQDataPointer = p_buffer;
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IRQDataSizeLeft = number_of_byte;
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IRQTaskWaitingHandle = xTaskGetCurrentTaskHandle();
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IRQFailureMarker = false;
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// Setup and run
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I2C_Init(I2C0_ID, I2C_WRITE, &i2cCfg); // Setup hardware for the I2C init header with the device address
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I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK);
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I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK);
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I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, UNMASK);
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I2C_Int_Callback_Install(I2C0_ID, I2C_TRANS_END_INT, i2c_irq_done);
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I2C_Int_Callback_Install(I2C0_ID, I2C_NACK_RECV_INT, i2c_irq_nack);
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I2C_Int_Callback_Install(I2C0_ID, I2C_TX_FIFO_READY_INT, i2c_irq_tx_fifo_low);
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CPU_Interrupt_Enable(I2C_IRQn);
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i2c_irq_tx_fifo_low();
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CPU_Interrupt_Disable(BLE_IRQn); // Shut up BLE while we do the transfer
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// Start
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I2C_Enable(I2C0_ID);
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// Wait for transfer in background
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uint32_t result = 0;
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xTaskNotifyWaitIndexed(I2C_NOTIFY_INDEX, 0xFFFFFFFF, 0xFFFFFFFF, &result, 0xFFFFFFFF);
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CPU_Interrupt_Enable(BLE_IRQn); // Now BLE can run
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return result == 1;
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}
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bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); }
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bool FRToSI2C::probe(uint16_t DevAddress) {
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uint8_t temp[1];
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return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
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}
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void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
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bool FRToSI2C::lock() {
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if (I2CSemaphore == nullptr) {
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return false;
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}
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return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE;
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}
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void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
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bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
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for (int index = 0; index < registersLength; index++) {
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if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
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return false;
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}
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if (registers[index].pause_ms) {
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delay_ms(registers[index].pause_ms);
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}
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}
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return true;
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}
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bool FRToSI2C::wakePart(uint16_t DevAddress) {
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// wakepart is a special case where only the device address is sent
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if (!lock()) {
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return false;
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}
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uint8_t temp[1] = {0};
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I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0};
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BL_Err_Type err = ERROR;
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i2cCfg.slaveAddr = DevAddress >> 1;
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i2cCfg.stopEveryByte = DISABLE;
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i2cCfg.subAddr = 0;
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i2cCfg.dataSize = 1;
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i2cCfg.data = temp;
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i2cCfg.subAddrSize = 0;
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err = I2C_MasterReceiveBlocking(I2C0_ID, &i2cCfg);
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bool res = err == SUCCESS;
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if (!res) {
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I2C_Unstick();
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}
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unlock();
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return res;
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}
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