ich777/IronOS
1
0
Fork 0
mirror of https://github.com/Ralim/IronOS.git synced 2025-07-23 12:23:06 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix RToS Update (#2091)

Browse Source 
* Silence undef

* Update Makefile

* Fix task priorities

* Bump CI host images

* Format c++

* Update make_translation.py

* Update bl702_common.c
This commit is contained in:
Ben V. Brown
2025-03-02 08:56:23 +11:00
committed by GitHub
parent 7ec1ece1a2
commit 08002e0d33
29 changed files with 94 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
.github/workflows/push.yml vendored
View File

@@ -10,9 +10,9 @@ on:
jobs:
build:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
strategy:
matrix:
model:
@@ -70,9 +70,9 @@ jobs:
if-no-files-found: error
build_multi-lang:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
strategy:
matrix:
model: ["Pinecil", "Pinecilv2"]
@@ -136,9 +136,9 @@ jobs:
if-no-files-found: error
tests:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
steps:
- name: Install dependencies (apk)
@@ -158,9 +158,9 @@ jobs:
run: make -C source/ Objects/host/brieflz/libbrieflz.so && ./Translations/brieflz_test.py
check_c-cpp:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
steps:
- name: Install dependencies (apk)
@@ -174,9 +174,9 @@ jobs:
run: make clean check-style
check_python:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
steps:
- name: Install dependencies (apk)
@@ -209,9 +209,9 @@ jobs:
check_all_files_with_shebangs: "false" # Optional.
check_docs:
runs-on: ubuntu-22.04
runs-on: ubuntu-24.04
container:
image: alpine:3.19
image: alpine:3.21
steps:
- name: Install dependencies (apk)

6
Translations/make_translation.py
View File

@@ -629,7 +629,7 @@ def make_font_table_named_cpp(
if name:
output_table = f"const uint8_t {name}[] = {{\n"
for i, sym in enumerate(sym_list):
output_table += f"{bytes_to_c_hex(font_map[sym])}//0x{i+2:X} -> {sym}\n"
output_table += f"{bytes_to_c_hex(font_map[sym])}//0x{i + 2:X} -> {sym}\n"
if name:
output_table += f"}}; // {name}\n"
return output_table
@@ -643,7 +643,7 @@ def make_font_table_06_cpp(sym_list: List[str], font_map: FontMapsPerFont) -> st
font_line = bytes_to_c_hex(font_bytes)
else:
font_line = "// " # placeholder
output_table += f"{font_line}//0x{i+2:X} -> {sym}\n"
output_table += f"{font_line}//0x{i + 2:X} -> {sym}\n"
output_table += "};\n"
return output_table
@@ -995,7 +995,7 @@ def write_languages(
f.write("};\n")
f.write(
"const uint8_t LanguageCount = sizeof(LanguageMetas) / sizeof(LanguageMetas[0]);\n\n"
f"alignas(TranslationData) uint8_t translation_data_out_buffer[{max_decompressed_translation_size }];\n"
f"alignas(TranslationData) uint8_t translation_data_out_buffer[{max_decompressed_translation_size}];\n"
"const uint16_t translation_data_out_buffer_size = sizeof(translation_data_out_buffer);\n\n"
)

2
source/Core/BSP/MHP30/FreeRTOSConfig.h
View File

@@ -101,7 +101,7 @@ extern uint32_t SystemCoreClock;
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES (6)
#define configMAX_PRIORITIES (7)
#define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN (32)

2
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c vendored
View File

@@ -182,7 +182,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;

2
source/Core/BSP/Miniware/FreeRTOSConfig.h
View File

@@ -101,7 +101,7 @@ extern uint32_t SystemCoreClock;
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (6)
#define configMAX_PRIORITIES (7)
#define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN (32)

2
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c vendored
View File

@@ -198,7 +198,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;

2
source/Core/BSP/Pinecil/FreeRTOSConfig.h
View File

@@ -8,7 +8,7 @@
#define configCPU_CLOCK_HZ ((uint32_t)SystemCoreClock)
#define configRTC_CLOCK_HZ ((uint32_t)32768)
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES (4)
#define configMAX_PRIORITIES (7)
#define configMINIMAL_STACK_SIZE ((unsigned short)128)
#define configMAX_TASK_NAME_LEN 24
#define configIDLE_SHOULD_YIELD 0

6
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c vendored
View File

@@ -632,7 +632,7 @@ uint32_t adc_sync_mode_convert_value_read(void) {
\retval none
*/
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) {
ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
/* analog watchdog channel select */
ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
@@ -650,7 +650,7 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel
\retval none
*/
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) {
ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
/* select the group */
switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL:
@@ -676,7 +676,7 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_
\param[out] none
\retval none
*/
void adc_watchdog_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); }
void adc_watchdog_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); }
/*!
\brief configure ADC analog watchdog threshold

3
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c vendored
View File

@@ -45,8 +45,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void bkp_deinit(void) { /* reset BKP domain register*/
}
void bkp_deinit(void) { /* reset BKP domain register*/ }
/*!
\brief write BKP data register

2
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c vendored
View File

@@ -112,7 +112,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
/* clear relative bits */
snctl &= ((uint32_t) ~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
snctl |= (uint32_t)((uint32_t)exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width |
exmc_norsram_init_struct->nwait_polarity | ((uint32_t)exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |

9
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c vendored
View File

@@ -519,8 +519,7 @@ void _premain_init(void) {
* by __libc_fini_array function, so we defined a new function
* to do initialization
*/
void _postmain_fini(int status) { /* TODO: Add your own finishing code here, called after main */
}
void _postmain_fini(int status) { /* TODO: Add your own finishing code here, called after main */ }
/**
* \brief _init function called in __libc_init_array()
@@ -531,8 +530,7 @@ void _postmain_fini(int status) { /* TODO: Add your own finishing code here, cal
* \note
* Please use \ref _premain_init function now
*/
void _init(void) { /* Don't put any code here, please use _premain_init now */
}
void _init(void) { /* Don't put any code here, please use _premain_init now */ }
/**
* \brief _fini function called in __libc_fini_array()
@@ -543,7 +541,6 @@ void _init(void) { /* Don't put any code here, please use _premain_init now */
* \note
* Please use \ref _postmain_fini function now
*/
void _fini(void) { /* Don't put any code here, please use _postmain_fini now */
}
void _fini(void) { /* Don't put any code here, please use _postmain_fini now */ }
/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */

3
source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/buf.c
View File

@@ -343,8 +343,7 @@ static u8_t *fixed_data_alloc(struct net_buf *buf, size_t *size, s32_t timeout)
return fixed->data_pool + fixed->data_size * net_buf_id(buf);
}
static void fixed_data_unref(struct net_buf *buf, u8_t *data) { /* Nothing needed for fixed-size data pools */
}
static void fixed_data_unref(struct net_buf *buf, u8_t *data) { /* Nothing needed for fixed-size data pools */ }
const struct net_buf_data_cb net_buf_fixed_cb = {
.alloc = fixed_data_alloc,

10
source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/att.c
View File

@@ -2059,14 +2059,14 @@ void bt_att_mtu_changed(struct bt_l2cap_chan *chan, u16_t mtu) { bt_gatt_mtu_cha
static int bt_att_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) {
int i;
static struct bt_l2cap_chan_ops ops = {
.connected = bt_att_connected,
.disconnected = bt_att_disconnected,
.recv = bt_att_recv,
.connected = bt_att_connected,
.disconnected = bt_att_disconnected,
.recv = bt_att_recv,
#if defined(CONFIG_BT_SMP)
.encrypt_change = bt_att_encrypt_change,
.encrypt_change = bt_att_encrypt_change,
#endif /* CONFIG_BT_SMP */
#if defined(BFLB_BLE_MTU_CHANGE_CB)
.mtu_changed = bt_att_mtu_changed,
.mtu_changed = bt_att_mtu_changed,
#endif
};

16
source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hci_core.c
View File

@@ -260,7 +260,11 @@ struct event_handler {
};
#define EVENT_HANDLER(_evt, _handler, _min_len) \
{ .event = _evt, .handler = _handler, .min_len = _min_len, }
{ \
.event = _evt, \
.handler = _handler, \
.min_len = _min_len, \
}
static inline void handle_event(u8_t event, struct net_buf *buf, const struct event_handler *handlers, size_t num_handlers) {
size_t i;
@@ -5240,11 +5244,11 @@ int bt_recv(struct net_buf *buf) {
}
static const struct event_handler prio_events[] = {
EVENT_HANDLER(BT_HCI_EVT_CMD_COMPLETE, hci_cmd_complete, sizeof(struct bt_hci_evt_cmd_complete)),
EVENT_HANDLER(BT_HCI_EVT_CMD_STATUS, hci_cmd_status, sizeof(struct bt_hci_evt_cmd_status)),
EVENT_HANDLER(BT_HCI_EVT_CMD_COMPLETE, hci_cmd_complete, sizeof(struct bt_hci_evt_cmd_complete)),
EVENT_HANDLER(BT_HCI_EVT_CMD_STATUS, hci_cmd_status, sizeof(struct bt_hci_evt_cmd_status)),
#if defined(CONFIG_BT_CONN)
EVENT_HANDLER(BT_HCI_EVT_DATA_BUF_OVERFLOW, hci_data_buf_overflow, sizeof(struct bt_hci_evt_data_buf_overflow)),
EVENT_HANDLER(BT_HCI_EVT_NUM_COMPLETED_PACKETS, hci_num_completed_packets, sizeof(struct bt_hci_evt_num_completed_packets)),
EVENT_HANDLER(BT_HCI_EVT_DATA_BUF_OVERFLOW, hci_data_buf_overflow, sizeof(struct bt_hci_evt_data_buf_overflow)),
EVENT_HANDLER(BT_HCI_EVT_NUM_COMPLETED_PACKETS, hci_num_completed_packets, sizeof(struct bt_hci_evt_num_completed_packets)),
#endif /* CONFIG_BT_CONN */
};
@@ -5618,7 +5622,7 @@ extern struct net_buf_pool prep_pool;
#if defined(CONFIG_BT_BREDR)
extern struct net_buf_pool br_sig_pool;
extern struct net_buf_pool sdp_pool;
#if defined CONFIG_BT_HFP
#if defined CONFIG_BT_HFP
extern struct net_buf_pool hf_pool;
extern struct net_buf_pool dummy_pool;
#endif

5
source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c
View File

@@ -55,8 +55,9 @@
#ifndef __GNUC__
__WEAK
__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt){
lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0,
r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr}
lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2,
# 0x01 cmp r2, #0x00 bne loop end bx lr
}
#else
__WEAK
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) {

3
source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c
View File

@@ -1404,8 +1404,7 @@ BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) {
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void) { /* TODO: Not implemented */
}
void SF_Ctrl_IRQHandler(void) { /* TODO: Not implemented */ }
#endif
/*@} end of group SF_CTRL_Public_Functions */

2
source/Core/BSP/Sequre/FreeRTOSConfig.h
View File

@@ -101,7 +101,7 @@ extern uint32_t SystemCoreClock;
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ (1000)
#define configMAX_PRIORITIES (6)
#define configMAX_PRIORITIES (7)
#define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN (32)

3
source/Core/BSP/Sequre/Setup.cpp
View File

@@ -319,6 +319,9 @@ static void MX_TIM2_Init(void) {
TIM_ClockConfigTypeDef sClockSourceConfig;
TIM_MasterConfigTypeDef sMasterConfig;
TIM_OC_InitTypeDef sConfigOC;
memset(&sConfigOC, 0, sizeof(sConfigOC));
memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig));
memset(&sMasterConfig, 0, sizeof(sMasterConfig));
// Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC
// in the PWM off time.

2
source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c vendored
View File

@@ -198,7 +198,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;

6
source/Core/Drivers/BMA223.cpp
View File

@@ -22,8 +22,8 @@ bool BMA223::detect() {
}
static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
//
//
//
//
{ BMA223_PMU_RANGE, 0b00000011, 0}, // 2G range
{ BMA223_PMU_BW, 0b00001101, 0}, // 250Hz filter
{ BMA223_PMU_LPW, 0b00000000, 0}, // Full power
@@ -33,7 +33,7 @@ static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
{ BMA223_INT_EN_0, 0b01000000, 0}, // Enable orientation
{ BMA223_INT_A, 0b00100111, 0}, // Setup orientation detection
//
//
};
bool BMA223::initalize() {
// Setup acceleration readings

2
source/Core/Drivers/LIS2DH12.cpp
View File

@@ -17,7 +17,7 @@ static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
{ LIS_CTRL_REG4, 0b00001000, 0}, // Block update mode off, HR on
{ LIS_CTRL_REG5, 0b00000010, 0}, //
{ LIS_CTRL_REG6, 0b01100010, 0},
// Basically setup the unit to run, and enable 4D orientation detection
// Basically setup the unit to run, and enable 4D orientation detection
{ LIS_INT2_CFG, 0b01111110, 0}, // setup for movement detection
{ LIS_INT2_THS, 0x28, 0}, //
{LIS_INT2_DURATION, 64, 0}, //

4
source/Core/Drivers/MSA301.cpp
View File

@@ -13,8 +13,8 @@
bool MSA301::detect() { return ACCEL_I2C_CLASS::probe(MSA301_I2C_ADDRESS); }
static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
//
//
//
//
{ MSA301_REG_ODR, 0b00001000, 1}, // X/Y/Z enabled @ 250Hz
{MSA301_REG_POWERMODE, 0b0001001, 1}, // Normal mode
{ MSA301_REG_RESRANGE, 0b00000001, 0}, // 14bit resolution @ 4G range

2
source/Core/Drivers/OLED.cpp
View File

@@ -34,7 +34,7 @@ uint32_t OLED::displayChecksum;
* Data packets are prefixed with 0x40
*/
I2C_CLASS::I2C_REG OLED_Setup_Array[] = {
/**/
/**/
{0x80, OLED_OFF, 0}, /* Display off */
{0x80, OLED_DIVIDER, 0}, /* Set display clock divide ratio / osc freq */
{0x80, 0x52, 0}, /* Divide ratios */

10
source/Core/Drivers/SC7A20.cpp
View File

@@ -42,15 +42,15 @@ bool SC7A20::detect() {
}
static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
//
//
//
//
{ SC7A20_CTRL_REG1, 0b01100111, 0}, // 200Hz, XYZ enabled
{ SC7A20_CTRL_REG2, 0b00000000, 0}, // Setup filter to 0x00 ??
{ SC7A20_CTRL_REG3, 0b00000000, 0}, // int1 off
{ SC7A20_CTRL_REG4, 0b01001000, 0}, // Block mode off,little-endian,2G,High-pres,self test off
{ SC7A20_CTRL_REG5, 0b00000100, 0}, // fifo off, D4D on int1
{ SC7A20_CTRL_REG6, 0x00, 0}, // INT2 off
// Basically setup the unit to run, and enable 4D orientation detection
// Basically setup the unit to run, and enable 4D orientation detection
{ SC7A20_INT2_CFG, 0b01111110, 0}, // setup for movement detection
{ SC7A20_INT2_THS, 0x28, 0}, //
{SC7A20_INT2_DURATION, 64, 0}, //
@@ -58,7 +58,7 @@ static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
{ SC7A20_INT1_THS, 0x28, 0}, //
{SC7A20_INT1_DURATION, 64, 0}
//
//
};
static const ACCEL_I2C_CLASS::I2C_REG i2c_registers_alt[] = {
{ LIS_CTRL_REG1, 0b00110111, 0}, // 200Hz XYZ
@@ -67,7 +67,7 @@ static const ACCEL_I2C_CLASS::I2C_REG i2c_registers_alt[] = {
{ LIS_CTRL_REG4, 0b00001000, 0}, // Block update mode off, HR on
{ LIS_CTRL_REG5, 0b00000010, 0}, //
{ LIS_CTRL_REG6, 0b01100010, 0},
// Basically setup the unit to run, and enable 4D orientation detection
// Basically setup the unit to run, and enable 4D orientation detection
{ LIS_INT2_CFG, 0b01111110, 0}, // setup for movement detection
{ LIS_INT2_THS, 0x28, 0}, //
{LIS_INT2_DURATION, 64, 0}, //

2
source/Core/Src/Settings.cpp
View File

@@ -54,7 +54,7 @@ typedef struct {
} SettingConstants;
static const SettingConstants settingsConstants[(int)SettingsOptions::SettingsOptionsLength] = {
//{ min, max, increment, default}
//{ min, max, increment, default}
{ MIN_TEMP_C, MAX_TEMP_F, 5, SOLDERING_TEMP}, // SolderingTemp
{ MIN_TEMP_C, MAX_TEMP_F, 5, 150}, // SleepTemp
{ 0, 15, 1, SLEEP_TIME}, // SleepTime

6
source/Core/Src/settingsGUI.cpp
View File

@@ -450,11 +450,11 @@ const menuitem advancedMenu[] = {
/* clang-format on */
const menuitem *subSettingsMenus[] {
const menuitem *subSettingsMenus[]{
#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
powerMenu,
powerMenu,
#endif
solderingMenu, PowerSavingMenu, UIMenu, advancedMenu,
solderingMenu, PowerSavingMenu, UIMenu, advancedMenu,
};
/* ^^^ !!!ENABLE CLANG-FORMAT back!!! ^^^ */

2
source/Core/brieflz/brieflz.c
View File

@@ -65,7 +65,7 @@ typedef uint32_t blz_word;
#define LOOKUP_SIZE (1UL << BLZ_HASH_BITS)
#define NO_MATCH_POS ((blz_word)-1)
#define NO_MATCH_POS ((blz_word) - 1)
// Internal data structure
struct blz_state {

44
source/Core/brieflz/depack.c
View File

@@ -37,7 +37,7 @@ struct blz_state {
#if !defined(BLZ_NO_LUT)
static const unsigned char blz_gamma_lookup[256][2] = {
/* 00xxxxxx = 2 */
/* 00xxxxxx = 2 */
{ 2, 2},
{ 2, 2},
{ 2, 2},
@@ -103,7 +103,7 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 2, 2},
{ 2, 2},
/* 0100xxxx = 4 */
/* 0100xxxx = 4 */
{ 4, 4},
{ 4, 4},
{ 4, 4},
@@ -121,31 +121,31 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 4, 4},
{ 4, 4},
/* 010100xx = 8 */
/* 010100xx = 8 */
{ 8, 6},
{ 8, 6},
{ 8, 6},
{ 8, 6},
/* 01010100 = 16 01010101 = 16+ 01010110 = 17 01010111 = 17+ */
/* 01010100 = 16 01010101 = 16+ 01010110 = 17 01010111 = 17+ */
{16, 8},
{16, 0},
{17, 8},
{17, 0},
/* 010110xx = 9 */
/* 010110xx = 9 */
{ 9, 6},
{ 9, 6},
{ 9, 6},
{ 9, 6},
/* 01011100 = 18 01011101 = 18+ 01011110 = 19 01011111 = 19+ */
/* 01011100 = 18 01011101 = 18+ 01011110 = 19 01011111 = 19+ */
{18, 8},
{18, 0},
{19, 8},
{19, 0},
/* 0110xxxx = 5 */
/* 0110xxxx = 5 */
{ 5, 4},
{ 5, 4},
{ 5, 4},
@@ -163,31 +163,31 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 5, 4},
{ 5, 4},
/* 011100xx = 10 */
/* 011100xx = 10 */
{10, 6},
{10, 6},
{10, 6},
{10, 6},
/* 01110100 = 20 01110101 = 20+ 01110110 = 21 01110111 = 21+ */
/* 01110100 = 20 01110101 = 20+ 01110110 = 21 01110111 = 21+ */
{20, 8},
{20, 0},
{21, 8},
{21, 0},
/* 011110xx = 11 */
/* 011110xx = 11 */
{11, 6},
{11, 6},
{11, 6},
{11, 6},
/* 01111100 = 22 01111101 = 22+ 01111110 = 23 01111111 = 23+ */
/* 01111100 = 22 01111101 = 22+ 01111110 = 23 01111111 = 23+ */
{22, 8},
{22, 0},
{23, 8},
{23, 0},
/* 10xxxxxx = 3 */
/* 10xxxxxx = 3 */
{ 3, 2},
{ 3, 2},
{ 3, 2},
@@ -253,7 +253,7 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 3, 2},
{ 3, 2},
/* 1100xxxx = 6 */
/* 1100xxxx = 6 */
{ 6, 4},
{ 6, 4},
{ 6, 4},
@@ -271,31 +271,31 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 6, 4},
{ 6, 4},
/* 110100xx = 12 */
/* 110100xx = 12 */
{12, 6},
{12, 6},
{12, 6},
{12, 6},
/* 11010100 = 24 11010101 = 24+ 11010110 = 25 11010111 = 25+ */
/* 11010100 = 24 11010101 = 24+ 11010110 = 25 11010111 = 25+ */
{24, 8},
{24, 0},
{25, 8},
{25, 0},
/* 110110xx = 13 */
/* 110110xx = 13 */
{13, 6},
{13, 6},
{13, 6},
{13, 6},
/* 11011100 = 26 11011101 = 26+ 11011110 = 27 11011111 = 27+ */
/* 11011100 = 26 11011101 = 26+ 11011110 = 27 11011111 = 27+ */
{26, 8},
{26, 0},
{27, 8},
{27, 0},
/* 1110xxxx = 7 */
/* 1110xxxx = 7 */
{ 7, 4},
{ 7, 4},
{ 7, 4},
@@ -313,25 +313,25 @@ static const unsigned char blz_gamma_lookup[256][2] = {
{ 7, 4},
{ 7, 4},
/* 111100xx = 14 */
/* 111100xx = 14 */
{14, 6},
{14, 6},
{14, 6},
{14, 6},
/* 11110100 = 28 11110101 = 28+ 11110110 = 29 11110111 = 29+ */
/* 11110100 = 28 11110101 = 28+ 11110110 = 29 11110111 = 29+ */
{28, 8},
{28, 0},
{29, 8},
{29, 0},
/* 111110xx = 15 */
/* 111110xx = 15 */
{15, 6},
{15, 6},
{15, 6},
{15, 6},
/* 11111100 = 30 11111101 = 30+ 11111110 = 31 11111111 = 31+ */
/* 11111100 = 30 11111101 = 30+ 11111110 = 31 11111111 = 31+ */
{30, 8},
{30, 0},
{31, 8},

2
source/Makefile
View File

@@ -425,6 +425,7 @@ CHECKOPTIONS=-Wtrigraphs \
-Wmissing-field-initializers \
-Wshadow \
-Wno-unused-parameter \
-Wno-undef \
-Wdouble-promotion
CHECKOPTIONS_C=$(CHECKOPTIONS) -Wbad-function-cast
@@ -454,6 +455,7 @@ CFLAGS=$(DEV_CFLAGS) \
-D${COMPILER} \
-MMD \
-std=gnu11 \
-g3 \
$(OPTIM) \
-T$(LDSCRIPT) \
-c