mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 20:20:40 +02:00
288 lines
4.8 KiB
C
288 lines
4.8 KiB
C
/*
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* CoreFreq
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* Copyright (C) 2015-2017 CYRIL INGENIERIE
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* Licenses: GPL2
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*/
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#define SHM_FILENAME "corefreq-shm"
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typedef struct
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{
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Bit64 OffLine __attribute__ ((aligned (64)));
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CLOCK Clock;
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unsigned int Toggle;
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struct
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{
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CPUID_0x00000000 StdFunc;
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CPUID_0x80000000 ExtFunc;
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unsigned int Microcode;
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struct {
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unsigned short int CfgLock : 1-0,
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IORedir : 2-1,
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Unused : 16-2;
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};
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unsigned short int CStateLimit,
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CStateInclude;
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} Query;
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CPUID_STRUCT CpuID[CPUID_MAX_FUNC];
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struct {
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unsigned int ApicID,
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CoreID,
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ThreadID;
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struct {
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Bit32 BSP,
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x2APIC;
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} MP;
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struct {
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unsigned int Set,
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Size;
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unsigned short LineSz,
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Part,
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Way;
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struct {
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unsigned short WriteBack: 1-0,
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Inclusive: 2-1,
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_pad16 : 16-2;
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} Feature;
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} Cache[CACHE_MAX_LEVEL];
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} Topology;
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struct {
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unsigned int TM1,
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TM2,
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Target,
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Limit[2];
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struct {
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unsigned int ClockMod : 16-0,
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Extended : 32-16;
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} DutyCycle;
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unsigned int PowerPolicy;
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} PowerThermal;
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struct FLIP_FLOP {
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struct
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{
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unsigned long long
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INST;
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struct {
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unsigned long long
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UCC,
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URC;
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} C0;
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unsigned long long
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C3,
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C6,
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C7,
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TSC,
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C1;
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} Delta;
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struct {
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double IPS,
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IPC,
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CPI,
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Turbo,
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C0,
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C3,
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C6,
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C7,
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C1;
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} State;
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struct {
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double Ratio,
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Freq;
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} Relative;
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struct {
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unsigned int Sensor,
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Temp,
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Trip;
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} Thermal;
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struct {
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int VID;
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double Vcore;
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} Voltage;
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struct {
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unsigned int SMI;
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struct {
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unsigned int LOCAL,
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UNKNOWN,
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PCISERR,
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IOCHECK;
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} NMI;
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} Counter;
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} FlipFlop[2];
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} CPU_STRUCT;
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typedef struct
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{
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volatile unsigned long long Sync,
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Room __attribute__ ((aligned (128)));
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FEATURES Features;
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Bit64 PowerNow __attribute__ ((aligned (64)));
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Bit64 ODCM __attribute__ ((aligned (64)));
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Bit64 ODCM_Mask __attribute__ ((aligned (64)));
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Bit64 PowerMgmt __attribute__ ((aligned (64)));
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Bit64 PowerMgmt_Mask __attribute__ ((aligned (64)));
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Bit64 SpeedStep __attribute__ ((aligned (64)));
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Bit64 SpeedStep_Mask __attribute__ ((aligned (64)));
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Bit64 TurboBoost __attribute__ ((aligned (64)));
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Bit64 TurboBoost_Mask __attribute__ ((aligned (64)));
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Bit64 C1E __attribute__ ((aligned (64)));
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Bit64 C1E_Mask __attribute__ ((aligned (64)));
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Bit64 C3A __attribute__ ((aligned (64)));
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Bit64 C3A_Mask __attribute__ ((aligned (64)));
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Bit64 C1A __attribute__ ((aligned (64)));
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Bit64 C1A_Mask __attribute__ ((aligned (64)));
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Bit64 C3U __attribute__ ((aligned (64)));
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Bit64 C3U_Mask __attribute__ ((aligned (64)));
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Bit64 C1U __attribute__ ((aligned (64)));
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Bit64 C1U_Mask __attribute__ ((aligned (64)));
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unsigned int SleepInterval;
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struct timespec BaseSleep;
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struct {
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unsigned int Count,
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OnLine;
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} CPU;
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unsigned int Boost[MAX_BOOST],
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PM_version;
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unsigned int Top;
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unsigned int Toggle;
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struct PKG_FLIP_FLOP {
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struct
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{
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unsigned long long PTSC,
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PC02,
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PC03,
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PC06,
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PC07,
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PC08,
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PC09,
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PC10;
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} Delta;
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struct
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{
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unsigned long long FC0;
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} Uncore;
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} FlipFlop[2];
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struct {
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double PC02,
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PC03,
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PC06,
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PC07,
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PC08,
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PC09,
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PC10;
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} State;
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struct {
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double Turbo,
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C0,
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C3,
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C6,
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C7,
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C1;
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} Avg;
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char Brand[64],
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Architecture[32];
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} PROC_STRUCT;
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typedef struct
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{
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struct {
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signed int Experimental, // 0: Disable, 1: Enable
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hotplug, // < 0: Disable, Other: Enable
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pci, // < 0: Disable, other: Enable
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nmi; // <> 0: Failed, == 0: Enable
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} Registration;
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struct {
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Bit64 Operation __attribute__ ((aligned (64)));
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IDLEDRIVER IdleDriver;
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unsigned int tickReset,
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tickStep;
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pid_t trackTask;
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int sortByField,
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reverseOrder,
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taskCount;
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TASK_MCB taskList[PID_MAX_DEFAULT];
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MEM_MCB memInfo;
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struct {
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unsigned short version,
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major,
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minor;
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} kernel;
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char sysname[MAX_UTS_LEN],
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release[MAX_UTS_LEN],
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version[MAX_UTS_LEN],
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machine[MAX_UTS_LEN];
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} SysGate;
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struct {
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struct RING_CTRL {
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unsigned long arg;
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unsigned int cmd;
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} buffer[RING_SIZE];
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unsigned int head, tail;
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} Ring;
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char AppName[TASK_COMM_LEN];
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struct {
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struct
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{
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unsigned long long Speed;
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unsigned int Rate;
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} Bus;
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struct {
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struct {
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RAM_TIMING Timing;
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RAM_GEOMETRY DIMM[MC_MAX_DIMM];
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} Channel[MC_MAX_CHA];
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unsigned short SlotCount, ChannelCount;
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} MC[MC_MAX_CTRL];
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unsigned long long CtrlSpeed;
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unsigned short CtrlCount;
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struct {
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unsigned char // 00:MHz , 01:MT/s , 10:MB/s , 11:VOID
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Bus_Rate: 2-0,
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BusSpeed: 4-2,
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DDR_Rate: 6-4,
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DDRSpeed: 8-6;
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} Unit;
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} Uncore;
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PROC_STRUCT Proc;
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CPU_STRUCT Cpu[];
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} SHM_STRUCT;
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