mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 12:13:07 +02:00
566 lines
12 KiB
C
566 lines
12 KiB
C
/*
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* CoreFreq
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* Copyright (C) 2015-2017 CYRIL INGENIERIE
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* Licenses: GPL2
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*/
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typedef struct
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{
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struct
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{
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unsigned char Chr[4];
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} AX, BX, CX, DX;
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} BRAND;
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#define LEVEL_INVALID 0
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#define LEVEL_THREAD 1
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#define LEVEL_CORE 2
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typedef struct {
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union {
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struct
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{
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unsigned int
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SHRbits : 5-0,
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Unused1 : 32-5;
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};
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unsigned int Register;
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} AX;
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union {
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struct
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{
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unsigned int
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Threads : 16-0,
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Unused1 : 32-16;
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};
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unsigned int Register;
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} BX;
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union {
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struct
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{
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unsigned int
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Level : 8-0,
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Type : 16-8,
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Unused1 : 32-16;
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};
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unsigned int Register;
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} CX;
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union {
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struct
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{
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unsigned int
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x2ApicID: 32-0;
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};
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unsigned int Register;
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} DX;
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} CPUID_TOPOLOGY_LEAF;
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typedef struct
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{
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LOCAL_APIC Base;
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int ApicID,
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CoreID,
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ThreadID;
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struct CACHE_INFO
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{
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union
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{
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struct
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{ // Intel
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unsigned int
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Type : 5-0, // Cache Type *
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Level : 8-5, // Cache Level (starts at 1)
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Init : 9-8, // Self Init. cache level
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Assoc : 10-9, // Fully Associative cache
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Unused : 14-10,
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MxThrdID: 26-14, // Max threads for this cache
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MxCoreID: 32-26; // Max cores for this cache
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};
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struct
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{ // AMD L1
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unsigned int
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ISize : 8-0, // Inst. TLB number of entries
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IAssoc : 16-8, // Inst. TLB associativity
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DSize : 24-16, // Data TLB number of entries
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DAssoc : 32-24; // Data TLB associativity
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} CPUID_0x80000005_L1Tlb2and4M; // for 2 MB & 4 MB pages
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struct
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{ // AMD L2
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unsigned int
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ISize : 12-0,
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IAssoc : 16-12,
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DSize : 28-16,
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DAssoc : 32-28;
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} CPUID_0x80000006_L2ITlb2and4M;
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unsigned int AX;
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};
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union
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{
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struct
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{ // Intel
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unsigned int
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LineSz : 12-0, // L=System Coherency Line Size
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Part : 22-12, // P=Physical Line partitions
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Way : 32-22; // W=Ways of associativity
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};
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struct
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{ // AMD L1
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unsigned int
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ISize : 8-0, // Inst. TLB number of entries
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IAssoc : 16-8, // Inst. TLB associativity *
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DSize : 24-16, // Data TLB number of entries
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DAssoc : 32-24; // Data TLB associativity *
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} CPUID_0x80000005_L1Tlb4K; // for 4 KB pages
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struct
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{ // AMD L2
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unsigned int
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ISize : 12-0,
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IAssoc : 16-12,
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DSize : 28-16,
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DAssoc : 32-28;
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} CPUID_0x80000006_L2Tlb4K;
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unsigned int BX;
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};
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union
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{ // Intel
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unsigned int Set; // S=Number of Sets
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struct
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{ // AMD L1
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unsigned int
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LineSz : 8-0, // L1 data cache line size (B)
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ClPerTag: 16-8, // L1 data cache lines per tag
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Assoc : 24-16, // L1 data cache associativity*
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Size : 32-24; // L1 data cache size (KB)
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} CPUID_0x80000005_L1D;
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struct
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{ // AMD L2
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unsigned int
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LineSz : 8-0, // L2 cache line size (B)
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ClPerTag: 12-8, // L2 cache lines per tag
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Assoc : 16-12, // L2 cache associativity **
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Size : 32-16; // L2 cache size (KB) ***
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} CPUID_0x80000006_L2;
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unsigned int CX;
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};
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union
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{
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struct
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{ // Intel
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unsigned int
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WrBack : 1-0, // Write-Back **
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Inclus : 2-1, // Cache Inclusiveness ***
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Direct : 3-2, // Complex Cache Indexing ****
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Resrvd : 32-3;
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};
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struct
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{ // AMD L1
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unsigned int
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LineSz : 8-0, // L1 inst. cache line size (B)
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ClPerTag: 16-8, // L1 inst. cache lines per tag
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Assoc : 24-16, // L1 inst. cache associativity
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Size : 32-24; // L1 inst. cache size (KB)
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} CPUID_0x80000005_L1I;
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struct
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{ // AMD L3
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unsigned int
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LineSz : 8-0, // L3 cache line (B)
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ClPerTag: 12-8, // L3 cache lines per tag
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Assoc : 16-12, // L3 cache associativity
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Reserved: 18-16,
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Size : 32-18; // L3 cache size
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} CPUID_0x80000006_L3;
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unsigned int DX;
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};
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unsigned int Size;
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} Cache[CACHE_MAX_LEVEL];
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} CACHE_TOPOLOGY;
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/*
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--- Intel Cache Parameters Leaf ---
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* Cache Type Field
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0 = Null - No more caches
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1 = Data Cache
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2 = Instruction Cache
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3 = Unified Cache
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4-31 = Reserved
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** Write-Back Invalidate/Invalidate
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0 = WBINVD/INVD from threads sharing this cache
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acts upon lower level caches for threads sharing this cache.
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1 = WBINVD/INVD is not guaranteed to act upon lower level caches
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of non-originating threads sharing this cache.
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*** Cache Inclusiveness
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0 = Cache is not inclusive of lower cache levels.
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1 = Cache is inclusive of lower cache levels.
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**** Complex Cache Indexing
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0 = Direct mapped cache.
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1 = A complex function is used to index the cache,
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potentially using all address bits.
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--- AMD Cache Identifiers ---
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* L1 data cache associativity
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Bits Description
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00h Reserved
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01h 1 way (direct mapped)
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02h 2 way
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03h 3 way
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FEh-04h [L1IcAssoc] way
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FFh Fully associative
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** L2 cache associativity
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Bits Description Bits Description
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0h Disabled. 8h 16 ways
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1h 1 way (direct mapped) 9h Reserved
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2h 2 ways Ah 32 ways
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3h Reserved Bh 48 ways
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4h 4 ways Ch 64 ways
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5h Reserved Dh 96 ways
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6h 8 ways Eh 128 ways
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7h Reserved Fh Fully associative
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*** L2 cache size
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Bits Description
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03FFh-0000h Reserved
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0400h 1 MB
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07FFh-0401h Reserved
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0800h 2 MB
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FFFFh-0801h Reserved
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*/
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typedef struct
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{
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unsigned int Sensor,
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Target;
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struct {
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unsigned int
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TCC_Enable: 1-0,
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TM2_Enable: 2-1,
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TM_Select : 3-2,
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Trip : 4-3,
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Unused : 32-4;
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};
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CLOCK_MODULATION ClockModulation;
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ENERGY_PERF_BIAS PerfEnergyBias;
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MISC_PWR_MGMT PwrManagement;
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} POWER_THERMAL;
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typedef struct
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{
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struct // 64-byte cache line size.
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{
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unsigned long long V,
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_pad[7];
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} Sync;
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Bit64 OffLine __attribute__ ((aligned (64)));
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struct
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{
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unsigned long long INST;
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struct
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{
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unsigned long long
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UCC,
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URC;
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} C0;
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unsigned long long
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C3,
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C6,
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C7,
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TSC;
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unsigned long long C1;
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int VID;
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} Counter[2];
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struct
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{
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unsigned long long
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INST;
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struct
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{
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unsigned long long
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UCC,
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URC;
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} C0;
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unsigned long long
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C3,
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C6,
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C7,
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TSC,
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C1;
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unsigned int SMI;
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} Delta;
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POWER_THERMAL PowerThermal;
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struct
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{
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unsigned int SMI;
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struct {
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unsigned int
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LOCAL,
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UNKNOWN,
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PCISERR,
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IOCHECK;
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} NMI;
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} Interrupt;
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struct
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{
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CORE_GLOBAL_PERF_CONTROL Core_GlobalPerfControl;
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CORE_FIXED_PERF_CONTROL Core_FixedPerfControl;
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} SaveArea;
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struct
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{
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CPUID_0x00000000 StdFunc;
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CPUID_0x80000000 ExtFunc;
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struct {
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unsigned long long
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EIST : 1-0, // Package
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C1E : 2-1, // Package
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Turbo : 3-2, // Thread
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C3A : 4-3, // Core
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C1A : 5-4, // Core
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C3U : 6-5, // Sandy Bridge
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C1U : 7-6, // Sandy Bridge
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CfgLock : 8-7, // Core
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IORedir : 9-8, // Core
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Unused : 32-9,
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Microcode:64-32; // Thread
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};
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unsigned short int CStateLimit,
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CStateInclude;
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} Query;
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CPUID_STRUCT CpuID[CPUID_MAX_FUNC];
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CACHE_TOPOLOGY T;
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unsigned int Bind;
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CLOCK Clock;
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} CORE;
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typedef struct
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{
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struct {
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union {
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struct {
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/* 29Ch */ P965_MC_ODTCTRL DRT0; /* 32 bits */
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/* 250h */ P965_MC_CYCTRK_PCHG DRT1; /* 16 bits */
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/* 252h */ P965_MC_CYCTRK_ACT DRT2; /* 32 bits */
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/* 256h */ P965_MC_CYCTRK_WR DRT3; /* 16 bits */
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/* 258h */ P965_MC_CYCTRK_RD DRT4; /* 24 bits */
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} P965;
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struct {
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/* 1210h */ G965_MC_DRAM_TIMING_R0 DRT0; /* 32 bits */
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/* 1214h */ G965_MC_DRAM_TIMING_R1 DRT1; /* 32 bits */
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/* 1218h */ G965_MC_DRAM_TIMING_R2 DRT2; /* 32 bits */
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/* 121Ch */ G965_MC_DRAM_TIMING_R3 DRT3; /* 32 bits */
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} G965;
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struct {
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/* 265h */ P35_MC_UNKNOWN_R0 DRT0; /* 16 bits */
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/* 250h */ P35_MC_CYCTRK_PCHG DRT1; /* 16 bits */
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/* 252h */ P35_MC_CYCTRK_ACT DRT2; /* 32 bits */
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/* 256h */ P35_MC_CYCTRK_WR DRT3; /* 16 bits */
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/* 258h */ P35_MC_CYCTRK_RD DRT4; /* 24 bits */
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/* 25Dh */ P35_MC_UNKNOWN_R1 DRT5; /* 16 bits */
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} P35;
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struct {
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NHM_IMC_MRS_VALUE_0_1 MR0_1;
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NHM_IMC_MRS_VALUE_2_3 MR2_3;
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NHM_IMC_RANK_TIMING_A Rank_A;
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NHM_IMC_RANK_TIMING_B Rank_B;
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NHM_IMC_BANK_TIMING Bank;
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NHM_IMC_REFRESH_TIMING Refresh;
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NHM_IMC_SCHEDULER_PARAMS Params;
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} NHM;
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struct {
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/* 4000h */ C200_TC_DBP DBP; /* 32 bits */
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/* 4004h */ C200_TC_RAP RAP; /* 32 bits */
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/* 4298h */ C200_TC_RFTP RFTP; /* 32 bits */
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} C200;
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struct {
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/* 4C04h*/ C220_DDR_TIMING Timing; /* 32 bits */
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/* 4c14h */ C220_DDR_RANK_TIMING Rank; /* 32 bits */
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/* 4e98h */ C220_TC_REFRESH_TIMING Refresh; /*32 bits */
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} C220;
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struct {
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/* 88h */ AMD_0F_DRAM_TIMING_LOW DTRL; /* 32 bits */
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} AMD0F;
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};
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union {
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/* 1208h */ G965_MC_DRAM_RANK_ATTRIB DRA;
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/* 48h */ NHM_IMC_DOD_CHANNEL DOD; /* 32 bits */
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/* 40h*/ AMD_0F_DRAM_CS_BASE_ADDR MBA; /* 32 bits */
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} DIMM[MC_MAX_DIMM];
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} Channel[MC_MAX_CHA];
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union {
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struct {
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/* 260h */ P965_MC_CKECTRL CKE0, /* 32 bits */
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CKE1; /* 32 bits */
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} P965;
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struct {
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/* 1200h */ G965_MC_DRB_0_1 DRB0, /* 32 bits @ channel0 */
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/* 1300h*/ DRB1; /* 32 bits @ channel1 */
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} G965;
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struct {
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/* 260h */ P35_MC_CKECTRL CKE0, /* 32 bits */
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CKE1; /* 32 bits */
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} P35;
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struct {
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/* 3:0-48h */ NHM_IMC_CONTROL CONTROL; /* 32 bits */
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/* 3:0 4Ch*/ NHM_IMC_STATUS STATUS; /* 32 bits */
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} NHM;
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struct {
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/* 5004h */ C200_MAD_CHANNEL MAD0, /* 32 bits */
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/* 5008h */ MAD1; /* 32 bits */
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} C200;
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struct {
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/* 90h */ AMD_0F_DRAM_CONFIG_LOW DCRL; /* 32 bits */
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/* 94h */ AMD_0F_DRAM_CONFIG_HIGH DCRH; /* 32 bits */
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} AMD0F;
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};
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union {
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struct {
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/* 64h */ NHM_IMC_MAX_DOD DOD; /* 32 bits */
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} NHM;
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struct {
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/* 80h */ AMD_0F_DRAM_CS_MAPPING CS; /* 32 bits */
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} AMD0F;
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} MaxDIMMs;
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unsigned short SlotCount, ChannelCount;
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} MC_REGISTERS;
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typedef union
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{
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union {
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struct {
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MCH_CLKCFG ClkCfg;
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};
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struct {
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NHM_IMC_CLK_RATIO_STATUS DimmClock;
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X58_QPI_FREQUENCY QuickPath;
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};
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struct {
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AMD_0F_HTT_UNIT_ID UnitID;
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AMD_0F_HTT_FREQUENCY LDTi_Freq[3];
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};
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};
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} BUS_REGISTERS;
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typedef struct {
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IDLEDRIVER IdleDriver;
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int taskCount;
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TASK_MCB taskList[PID_MAX_DEFAULT];
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MEM_MCB memInfo;
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unsigned int kernelVersionNumber;
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char sysname[MAX_UTS_LEN],
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release[MAX_UTS_LEN],
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version[MAX_UTS_LEN],
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machine[MAX_UTS_LEN];
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} SYSGATE;
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|
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typedef struct
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{
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struct
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{
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unsigned long long PTSC, // Package Time Stamp Counter
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PC02, // Goldmont, Sandy-Bridge, Phi
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PC03, // Goldmont, Nehalem, Sandy-Bridge, Phi
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PC06, // Goldmont, Nehalem, Sandy-Bridge, Phi
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PC07, // Nehalem, Sandy-Bridge, Phi
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PC08, // Haswell
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PC09, // Haswell
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PC10; // Goldmont, Haswell
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struct {
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unsigned long long FC0; // Uncore fixed counter #0
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} Uncore;
|
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} Counter[2];
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|
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struct
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{
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unsigned long long PTSC,
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PC02,
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PC03,
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PC06,
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PC07,
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PC08,
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PC09,
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PC10;
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struct {
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unsigned long long FC0;
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} Uncore;
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} Delta;
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|
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struct
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{
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UNCORE_GLOBAL_PERF_CONTROL Uncore_GlobalPerfControl;
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UNCORE_FIXED_PERF_CONTROL Uncore_FixedPerfControl;
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} SaveArea;
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|
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FEATURES Features;
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|
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Bit64 ODCM_Mask __attribute__ ((aligned (64)));
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Bit64 PowerMgmt_Mask __attribute__ ((aligned (64)));
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Bit64 SpeedStep_Mask __attribute__ ((aligned (64)));
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Bit64 TurboBoost_Mask __attribute__ ((aligned (64)));
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Bit64 C1E_Mask __attribute__ ((aligned (64)));
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Bit64 C3A_Mask __attribute__ ((aligned (64))); // NHM
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Bit64 C1A_Mask __attribute__ ((aligned (64))); // NHM
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Bit64 C3U_Mask __attribute__ ((aligned (64))); // SNB
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Bit64 C1U_Mask __attribute__ ((aligned (64))); // SNB
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|
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unsigned long long thermalFormula,
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voltageFormula;
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|
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unsigned int SleepInterval,
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tickReset,
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tickStep;
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|
|
struct {
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unsigned int Count,
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OnLine;
|
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} CPU;
|
|
|
|
signed int ArchID;
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unsigned int Boost[MAX_BOOST];
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|
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struct {
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BUS_REGISTERS Bus;
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MC_REGISTERS MC[MC_MAX_CTRL];
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unsigned short CtrlCount;
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unsigned short ChipID;
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} Uncore;
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|
|
SYSGATE *SysGate;
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|
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struct {
|
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signed int Experimental,
|
|
hotplug,
|
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pci,
|
|
nmi;
|
|
} Registration;
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|
|
char Architecture[32];
|
|
} PROC;
|