mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 12:13:07 +02:00
208 lines
4.2 KiB
C
208 lines
4.2 KiB
C
/*
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* CoreFreq
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* Copyright (C) 2015-2017 CYRIL INGENIERIE
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* Licenses: GPL2
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*/
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typedef unsigned long long int Bit64;
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typedef unsigned int Bit32;
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#define LOCKLESS " "
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#define BUS_LOCK "lock "
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#define _BITSET_GPR(_lock, _base, _offset) \
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({ \
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asm volatile \
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( \
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_lock "btsq %%rdx, %[base]" \
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: [base] "=m" (_base) \
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: "d" (_offset) \
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: "cc", "memory" \
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); \
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})
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#define _BITSET_IMM(_lock, _base, _imm8) \
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({ \
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asm volatile \
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( \
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_lock "btsq %[imm8], %[base]" \
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: [base] "=m" (_base) \
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: [imm8] "i" (_imm8) \
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: "cc", "memory" \
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); \
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})
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#define _BITCLR_GPR(_lock, _base, _offset) \
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({ \
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asm volatile \
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( \
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_lock "btrq %%rdx, %[base]" \
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: [base] "=m" (_base) \
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: "d" (_offset) \
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: "cc", "memory" \
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); \
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})
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#define _BITCLR_IMM(_lock, _base, _imm8) \
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({ \
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asm volatile \
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( \
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_lock "btrq %[imm8], %[base]" \
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: [base] "=m" (_base) \
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: [imm8] "i" (_imm8) \
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: "cc", "memory" \
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); \
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})
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#define _BITBTC_GPR(_lock,_base, _offset) \
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({ \
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asm volatile \
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( \
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_lock "btcq %%rdx, %[base]" \
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: [base] "=m" (_base) \
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: "d" (_offset) \
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: "cc", "memory" \
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); \
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})
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#define _BITBTC_IMM(_lock, _base, _imm8) \
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({ \
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asm volatile \
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( \
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_lock "btcq %[imm8], %[base]" \
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: [base] "=m" (_base) \
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: [imm8] "i" (_imm8) \
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: "cc", "memory" \
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); \
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})
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#define _BIT_TEST_GPR(_base, _offset) \
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({ \
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register unsigned char _ret = 0; \
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asm volatile \
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( \
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"btq %%rdx, %[base]" "\n\t" \
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"setc %[ret]" \
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: [ret] "+r" (_ret) \
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: [base] "m" (_base), \
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"d" (_offset) \
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: "cc", "memory" \
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); \
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_ret; \
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})
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#define _BIT_TEST_IMM(_base, _imm8) \
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({ \
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register unsigned char _ret = 0; \
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asm volatile \
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( \
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"btq %[imm8], %[base]""\n\t" \
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"setc %[ret]" \
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: [ret] "+r" (_ret) \
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: [base] "m" (_base), \
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[imm8] "i" (_imm8) \
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: "cc", "memory" \
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); \
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_ret; \
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})
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#define _BITWISEAND(_lock, _opl, _opr) \
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({ \
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volatile Bit64 _ret __attribute__ ((aligned (64)))=_opl;\
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asm volatile \
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( \
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_lock "andq %[opr], %[ret]" \
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: [ret] "=m" (_ret) \
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: [opr] "Jr" (_opr) \
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: "memory" \
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); \
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_ret; \
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})
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#define _BITWISEOR(_lock, _opl, _opr) \
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({ \
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volatile Bit64 _ret __attribute__ ((aligned (64)))=_opl;\
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asm volatile \
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( \
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_lock "orq %[opr], %[ret]" \
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: [ret] "=m" (_ret) \
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: [opr] "Jr" (_opr) \
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: "memory" \
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); \
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_ret; \
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})
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#define _BITWISEXOR(_lock, _opl, _opr) \
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({ \
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volatile Bit64 _ret __attribute__ ((aligned (64)))=_opl;\
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asm volatile \
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( \
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_lock "xorq %[opr], %[ret]" \
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: [ret] "=m" (_ret) \
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: [opr] "Jr" (_opr) \
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: "memory" \
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); \
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_ret; \
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})
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#define BITMSK(_lock, _base, _offset) \
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({ \
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asm volatile \
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( \
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_lock "orq $0xffffffffffffffff, %[base]" "\n\t" \
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_lock "btc %[offset], %[base]" \
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: [base] "=m" (_base) \
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: [offset] "Jr" (_offset) \
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: "cc", "memory" \
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); \
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})
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#define BITSET(_lock, _base, _offset) \
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( \
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__builtin_constant_p(_offset) ? \
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_BITSET_IMM(_lock, _base, _offset) \
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: _BITSET_GPR(_lock, _base, _offset) \
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)
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#define BITCLR(_lock, _base, _offset) \
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( \
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__builtin_constant_p(_offset) ? \
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_BITCLR_IMM(_lock, _base, _offset) \
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: _BITCLR_GPR(_lock, _base, _offset) \
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)
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#define BITBTC(_lock, _base, _offset) \
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( \
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__builtin_constant_p(_offset) ? \
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_BITBTC_IMM(_lock, _base, _offset) \
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: _BITBTC_GPR(_lock, _base, _offset) \
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)
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#define BITVAL(_base, _offset) \
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( \
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__builtin_constant_p(_offset) ? \
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_BIT_TEST_IMM(_base, _offset) \
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: _BIT_TEST_GPR(_base, _offset) \
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)
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#define BITCPL(_src) \
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({ \
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unsigned long long _dest; \
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asm volatile \
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( \
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"mov %[src], %[dest]" "\n\t" \
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"negq %[dest]" \
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: [dest] "=m" (_dest) \
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: [src] "ir" (_src) \
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: "memory" \
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); \
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_dest; \
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})
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#define BITWISEAND(_lock, _opl, _opr) _BITWISEAND(_lock, _opl, _opr)
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#define BITWISEOR(_lock, _opl, _opr) _BITWISEOR(_lock, _opl, _opr)
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#define BITWISEXOR(_lock, _opl, _opr) _BITWISEXOR(_lock, _opl, _opr)
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#define BITSTOR(_lock, _dest, _src) \
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_dest = BITWISEAND(_lock, _src, 0xffffffffffffffff)
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