mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 20:20:40 +02:00
503 lines
17 KiB
C
503 lines
17 KiB
C
/*
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* CoreFreq
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* Copyright (C) 2015-2021 CYRIL INGENIERIE
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* Licenses: GPL2
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*/
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#define CLEAR_EVENT_MASK 0x0000000000000ff0
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#define TRACK_TASK 0x0200000000000000
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#define TRACK_MASK 0x00000000000fffff
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#define CPU_ONLINE 0x0000080000000000
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#define CPU_OFFLINE 0x0000100000000000
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#define CPU_STATE_MASK 0x0000180000000000
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#define CPU_SELECT 0x0000200000000000
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#define CPU_MASK 0x00000000000000ff
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#define RATIO_MASK 0x000000000000ffff
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#define BOXKEY_CSTATE_MASK 0x00000000000000f0
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#define BOXKEY_TURBO_CLOCK 0x00010000
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#define BOXKEY_TURBO_CLOCK_NC 0x00020000LLU
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#define BOXKEY_RATIO_CLOCK 0x00040000
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#define BOXKEY_RATIO_CLOCK_OR 0x00080000LLU
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#define BOXKEY_CFGTDP_CLOCK 0x00220000
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#define BOXKEY_CFGTDP_CLOCK_OR 0x00200000LLU
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#define BOXKEY_UNCORE_CLOCK 0x00400000
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#define BOXKEY_UNCORE_CLOCK_OR 0x00800000LLU
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#define BOXKEY_RATIO_SELECT_OR 0x08000000LLU
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#define CLOCKMOD_RATIO_MASK 0x0000ffff
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#define OPS_RECORDER_MASK 0x00000000000000f0LLU
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#define SMBIOS_STRING_INDEX 0x0010000000000000
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#define SMBIOS_STRING_MASK 0x00000000000000ffLLU
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#define BOXKEY_TDP_OR 0x3000000000021100
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#define BOXKEY_PL1_OR 0x3000000000021204
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#define BOXKEY_PL2_OR 0x3000000000021208
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#define BOXKEY_PLX_AND 0x3000000000021200
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#define BOXKEY_TDP_MASK 0x000000000000000f
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#define BOXKEY_PLX_MASK 0x000000000000000c
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#define BOXKEY_TDP_OFFSET 0x000000000ff00000
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enum {
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SORTBY_STATE = 0x010000000000000e,
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SORTBY_RTIME = 0x010000000000000d,
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SORTBY_UTIME = 0x010000000000000c,
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SORTBY_STIME = 0x010000000000000b,
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SORTBY_PID = 0x010000000000000a,
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SORTBY_COMM = 0x0100000000000009,
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OPS_INTERVAL = 0x1000000000001000,
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OPS_INTERVAL_100 = 0x1000000000001001,
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OPS_INTERVAL_150 = 0x1000000000001011,
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OPS_INTERVAL_250 = 0x1000000000001021,
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OPS_INTERVAL_500 = 0x1000000000001031,
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OPS_INTERVAL_750 = 0x1000000000001041,
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OPS_INTERVAL_1000 = 0x1000000000001051,
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OPS_INTERVAL_1500 = 0x1000000000001061,
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OPS_INTERVAL_2000 = 0x1000000000001071,
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OPS_INTERVAL_2500 = 0x1000000000001081,
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OPS_INTERVAL_3000 = 0x1000000000001091,
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OPS_AUTOCLOCK = 0x1000000000002000,
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OPS_AUTOCLOCK_OFF = 0x1000000000002001,
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OPS_AUTOCLOCK_ON = 0x1000000000002002,
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OPS_EXPERIMENTAL = 0x1000000000004000,
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OPS_EXPERIMENTAL_OFF = 0x1000000000004001,
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OPS_EXPERIMENTAL_ON = 0x1000000000004002,
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OPS_INTERRUPTS = 0x1000000000008000,
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OPS_INTERRUPTS_OFF = 0x1000000000008001,
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OPS_INTERRUPTS_ON = 0x1000000000008002,
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OPS_CPU_IDLE = 0x1000000000008010,
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OPS_CPU_IDLE_OFF = 0x1000000000008011,
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OPS_CPU_IDLE_ON = 0x1000000000008012,
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OPS_CPU_FREQ = 0x1000000000008020,
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OPS_CPU_FREQ_OFF = 0x1000000000008021,
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OPS_CPU_FREQ_ON = 0x1000000000008022,
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OPS_GOVERNOR = 0x1000000000008040,
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OPS_GOVERNOR_OFF = 0x1000000000008041,
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OPS_GOVERNOR_ON = 0x1000000000008042,
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OPS_CLOCK_SOURCE = 0x1000000000008080,
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OPS_CLOCK_SOURCE_OFF = 0x1000000000008081,
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OPS_CLOCK_SOURCE_ON = 0x1000000000008082,
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OPS_RECORDER = 0x1000000000010000,
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OPS_RECORDER_RESET = 0x1000000000010010,
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OPS_RECORDER_X002 = 0x1000000000010020,
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OPS_RECORDER_X010 = 0x1000000000010030,
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OPS_RECORDER_X020 = 0x1000000000010040,
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OPS_RECORDER_X060 = 0x1000000000010050,
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OPS_RECORDER_X090 = 0x1000000000010060,
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OPS_RECORDER_X120 = 0x1000000000010070,
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OPS_RECORDER_X240 = 0x1000000000010080,
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OPS_THERMAL_SCOPE = 0x1000000000020000,
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OPS_VOLTAGE_SCOPE = 0x1000000000021000,
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OPS_POWER_SCOPE = 0x1000000000022000,
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OPS_THERMAL_SCOPE_NONE = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_NONE),
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OPS_THERMAL_SCOPE_SMT = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_SMT),
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OPS_THERMAL_SCOPE_CORE = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_CORE),
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OPS_THERMAL_SCOPE_PKG = OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_PKG),
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OPS_VOLTAGE_SCOPE_NONE = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_NONE),
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OPS_VOLTAGE_SCOPE_SMT = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_SMT),
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OPS_VOLTAGE_SCOPE_CORE = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_CORE),
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OPS_VOLTAGE_SCOPE_PKG = OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_PKG),
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OPS_POWER_SCOPE_NONE = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_NONE),
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OPS_POWER_SCOPE_SMT = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_SMT),
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OPS_POWER_SCOPE_CORE = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_CORE),
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OPS_POWER_SCOPE_PKG = OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_PKG),
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BOXKEY_EIST = 0x3000000000000004,
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BOXKEY_EIST_OFF = 0x3000000000000005,
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BOXKEY_EIST_ON = 0x3000000000000006,
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BOXKEY_C1E = 0x3000000000000008,
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BOXKEY_C1E_OFF = 0x3000000000000009,
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BOXKEY_C1E_ON = 0x300000000000000a,
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BOXKEY_TURBO = 0x3000000000000010,
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BOXKEY_TURBO_OFF = 0x3000000000000011,
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BOXKEY_TURBO_ON = 0x3000000000000012,
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BOXKEY_C1A = 0x3000000000000020,
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BOXKEY_C1A_OFF = 0x3000000000000021,
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BOXKEY_C1A_ON = 0x3000000000000022,
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BOXKEY_C3A = 0x3000000000000040,
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BOXKEY_C3A_OFF = 0x3000000000000041,
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BOXKEY_C3A_ON = 0x3000000000000042,
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BOXKEY_C1U = 0x3000000000000080,
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BOXKEY_C1U_OFF = 0x3000000000000081,
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BOXKEY_C1U_ON = 0x3000000000000082,
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BOXKEY_C3U = 0x3000000000000100,
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BOXKEY_C3U_OFF = 0x3000000000000101,
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BOXKEY_C3U_ON = 0x3000000000000102,
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BOXKEY_PKGCST = 0x3000000000000200,
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BOXKEY_PKGCST_C0 = 0x3000000000000201 | ( _C0 << 4 ),
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BOXKEY_PKGCST_C1 = 0x3000000000000201 | ( _C1 << 4 ),
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BOXKEY_PKGCST_C2 = 0x3000000000000201 | ( _C2 << 4 ),
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BOXKEY_PKGCST_C3 = 0x3000000000000201 | ( _C3 << 4 ),
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BOXKEY_PKGCST_C4 = 0x3000000000000201 | ( _C4 << 4 ),
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BOXKEY_PKGCST_C6 = 0x3000000000000201 | ( _C6 << 4 ),
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BOXKEY_PKGCST_C6R = 0x3000000000000201 | ( _C6R << 4 ),
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BOXKEY_PKGCST_C7 = 0x3000000000000201 | ( _C7 << 4 ),
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BOXKEY_PKGCST_C7S = 0x3000000000000201 | ( _C7S << 4 ),
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BOXKEY_PKGCST_C8 = 0x3000000000000201 | ( _C8 << 4 ),
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BOXKEY_PKGCST_C9 = 0x3000000000000201 | ( _C9 << 4 ),
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BOXKEY_PKGCST_C10 = 0x3000000000000201 | ( _C10 << 4 ),
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BOXKEY_IOMWAIT = 0x3000000000000400,
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BOXKEY_IOMWAIT_OFF = 0x3000000000000401,
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BOXKEY_IOMWAIT_ON = 0x3000000000000402,
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BOXKEY_IORCST = 0x3000000000000800,
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BOXKEY_IORCST_C0 = 0x3000000000000801 | ( _C0 << 4 ),
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BOXKEY_IORCST_C3 = 0x3000000000000801 | ( _C3 << 4 ),
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BOXKEY_IORCST_C4 = 0x3000000000000801 | ( _C4 << 4 ),
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BOXKEY_IORCST_C6 = 0x3000000000000801 | ( _C6 << 4 ),
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BOXKEY_IORCST_C7 = 0x3000000000000801 | ( _C7 << 4 ),
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BOXKEY_IORCST_C8 = 0x3000000000000801 | ( _C8 << 4 ),
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BOXKEY_ODCM = 0x3000000000001000,
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BOXKEY_ODCM_OFF = 0x3000000000001001,
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BOXKEY_ODCM_ON = 0x3000000000001002,
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BOXKEY_DUTYCYCLE = 0x3000000000001100,
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BOXKEY_ODCM_DC00 = 0x3000000000001101,
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BOXKEY_ODCM_DC01 = 0x3000000000001111,
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BOXKEY_ODCM_DC02 = 0x3000000000001121,
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BOXKEY_ODCM_DC03 = 0x3000000000001131,
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BOXKEY_ODCM_DC04 = 0x3000000000001141,
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BOXKEY_ODCM_DC05 = 0x3000000000001151,
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BOXKEY_ODCM_DC06 = 0x3000000000001161,
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BOXKEY_ODCM_DC07 = 0x3000000000001171,
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BOXKEY_ODCM_DC08 = 0x3000000000001181,
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BOXKEY_ODCM_DC09 = 0x3000000000001191,
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BOXKEY_ODCM_DC10 = 0x30000000000011a1,
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BOXKEY_ODCM_DC11 = 0x30000000000011b1,
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BOXKEY_ODCM_DC12 = 0x30000000000011c1,
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BOXKEY_ODCM_DC13 = 0x30000000000011d1,
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BOXKEY_ODCM_DC14 = 0x30000000000011e1,
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BOXKEY_PWR_POLICY = 0x3000000000002100,
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BOXKEY_PWR_POL00 = 0x3000000000002101,
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BOXKEY_PWR_POL01 = 0x3000000000002111,
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BOXKEY_PWR_POL02 = 0x3000000000002121,
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BOXKEY_PWR_POL03 = 0x3000000000002131,
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BOXKEY_PWR_POL04 = 0x3000000000002141,
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BOXKEY_PWR_POL05 = 0x3000000000002151,
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BOXKEY_PWR_POL06 = 0x3000000000002161,
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BOXKEY_PWR_POL07 = 0x3000000000002171,
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BOXKEY_PWR_POL08 = 0x3000000000002181,
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BOXKEY_PWR_POL09 = 0x3000000000002191,
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BOXKEY_PWR_POL10 = 0x30000000000021a1,
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BOXKEY_PWR_POL11 = 0x30000000000021b1,
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BOXKEY_PWR_POL12 = 0x30000000000021c1,
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BOXKEY_PWR_POL13 = 0x30000000000021d1,
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BOXKEY_PWR_POL14 = 0x30000000000021e1,
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BOXKEY_PWR_POL15 = 0x30000000000021f1,
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BOXKEY_CC6 = 0x3000000000004000,
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BOXKEY_CC6_OFF = 0x3000000000004001,
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BOXKEY_CC6_ON = 0x3000000000004002,
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BOXKEY_PC6 = 0x3000000000004010,
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BOXKEY_PC6_OFF = 0x3000000000004011,
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BOXKEY_PC6_ON = 0x3000000000004012,
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BOXKEY_HWP = 0x3000000000004020,
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BOXKEY_HWP_ON = 0x3000000000004021,
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BOXKEY_HWP_EPP = 0x3000000000004040,
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BOXKEY_HWP_EPP_MIN = 0x3000000000004041,
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BOXKEY_HWP_EPP_020 = 0x3000000000004042,
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BOXKEY_HWP_EPP_040 = 0x3000000000004043,
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BOXKEY_HWP_EPP_060 = 0x3000000000004044,
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BOXKEY_HWP_EPP_MED = 0x3000000000004045,
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BOXKEY_HWP_EPP_0A0 = 0x3000000000004046,
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BOXKEY_HWP_EPP_PWR = 0x3000000000004047,
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BOXKEY_HWP_EPP_0E0 = 0x3000000000004048,
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BOXKEY_HWP_EPP_MAX = 0x3000000000004049,
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BOXKEY_HDC = 0x3000000000004080,
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BOXKEY_HDC_OFF = 0x3000000000004081,
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BOXKEY_HDC_ON = 0x3000000000004082,
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BOXKEY_R2H = 0x3000000000004100,
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BOXKEY_R2H_OFF = 0x3000000000004101,
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BOXKEY_R2H_ON = 0x3000000000004102,
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BOXKEY_L1_HW_PREFETCH = 0x3000000000004200,
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BOXKEY_L1_HW_PREFETCH_OFF = 0x3000000000004201,
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BOXKEY_L1_HW_PREFETCH_ON = 0x3000000000004202,
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BOXKEY_L1_HW_IP_PREFETCH = 0x3000000000004210,
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BOXKEY_L1_HW_IP_PREFETCH_OFF = 0x3000000000004211,
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BOXKEY_L1_HW_IP_PREFETCH_ON = 0x3000000000004212,
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BOXKEY_L2_HW_PREFETCH = 0x3000000000004220,
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BOXKEY_L2_HW_PREFETCH_OFF = 0x3000000000004221,
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BOXKEY_L2_HW_PREFETCH_ON = 0x3000000000004222,
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BOXKEY_L2_HW_CL_PREFETCH = 0x3000000000004240,
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BOXKEY_L2_HW_CL_PREFETCH_OFF = 0x3000000000004241,
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BOXKEY_L2_HW_CL_PREFETCH_ON = 0x3000000000004242,
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BOXKEY_CFG_TDP_LVL = 0x3000000000004280,
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BOXKEY_CFG_TDP_LVL0 = 0x3000000000004281,
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BOXKEY_CFG_TDP_LVL1 = 0x3000000000004282,
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BOXKEY_CFG_TDP_LVL2 = 0x3000000000004283,
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BOXKEY_TOOLS_MACHINE = 0x3000000000010000,
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BOXKEY_TOOLS_ATOMIC = 0x3000000000010010,
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BOXKEY_TOOLS_CRC32 = 0x3000000000010020,
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BOXKEY_TOOLS_CONIC = 0x3000000000011000,
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BOXKEY_TOOLS_CONIC0 = 0x3000000000011401,
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BOXKEY_TOOLS_CONIC1 = 0x3000000000011411,
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BOXKEY_TOOLS_CONIC2 = 0x3000000000011421,
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BOXKEY_TOOLS_CONIC3 = 0x3000000000011431,
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BOXKEY_TOOLS_CONIC4 = 0x3000000000011441,
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BOXKEY_TOOLS_CONIC5 = 0x3000000000011451,
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BOXKEY_TOOLS_TURBO_RND = 0x3000000000012001,
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BOXKEY_TOOLS_TURBO_RR = 0x3000000000012011,
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BOXKEY_TOOLS_TURBO_CPU = 0x3000000000012021,
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BOXKEY_LANG_ENGLISH = 0x3000000000014021,
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BOXKEY_LANG_FRENCH = 0x3000000000014022,
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BOXKEY_LIMIT_IDLE_STATE = 0x3000000000014800,
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BOXKEY_LIMIT_IDLE_ST00 = 0x3000000000014801,
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BOXKEY_LIMIT_IDLE_ST01 = 0x3000000000014811,
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BOXKEY_LIMIT_IDLE_ST02 = 0x3000000000014821,
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BOXKEY_LIMIT_IDLE_ST03 = 0x3000000000014831,
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BOXKEY_LIMIT_IDLE_ST04 = 0x3000000000014841,
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BOXKEY_LIMIT_IDLE_ST05 = 0x3000000000014851,
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BOXKEY_LIMIT_IDLE_ST06 = 0x3000000000014861,
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BOXKEY_LIMIT_IDLE_ST07 = 0x3000000000014871,
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BOXKEY_LIMIT_IDLE_ST08 = 0x3000000000014881,
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BOXKEY_LIMIT_IDLE_ST09 = 0x3000000000014891,
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BOXKEY_LIMIT_IDLE_ST10 = 0x30000000000148a1,
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BOXKEY_CLR_THM_SENSOR = 0x3000000000020011,
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BOXKEY_CLR_THM_PROCHOT = 0x3000000000020021,
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BOXKEY_CLR_THM_CRIT = 0x3000000000020041,
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BOXKEY_CLR_THM_THOLD = 0x3000000000020081,
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BOXKEY_CLR_PWR_LIMIT = 0x3000000000020101,
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BOXKEY_CLR_CUR_LIMIT = 0x3000000000020201,
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BOXKEY_CLR_X_DOMAIN = 0x3000000000020401,
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BOXKEY_TDP_PKG = BOXKEY_TDP_OR | PWR_DOMAIN(PKG),
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BOXKEY_TDP_CORES = BOXKEY_TDP_OR | PWR_DOMAIN(CORES),
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BOXKEY_TDP_UNCORE = BOXKEY_TDP_OR | PWR_DOMAIN(UNCORE),
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BOXKEY_TDP_RAM = BOXKEY_TDP_OR | PWR_DOMAIN(RAM),
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BOXKEY_TDP_PLATFORM = BOXKEY_TDP_OR | PWR_DOMAIN(PLATFORM),
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BOXKEY_PL1_PKG_ON = BOXKEY_PL1_OR | (PWR_DOMAIN(PKG) << 4)|1,
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BOXKEY_PL1_PKG_OFF = BOXKEY_PL1_OR | (PWR_DOMAIN(PKG) << 4)|2,
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BOXKEY_PL1_CORES_ON = BOXKEY_PL1_OR | (PWR_DOMAIN(CORES) << 4)|1,
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BOXKEY_PL1_CORES_OFF = BOXKEY_PL1_OR | (PWR_DOMAIN(CORES) << 4)|2,
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BOXKEY_PL1_UNCORE_ON = BOXKEY_PL1_OR | (PWR_DOMAIN(UNCORE) << 4)|1,
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BOXKEY_PL1_UNCORE_OFF = BOXKEY_PL1_OR | (PWR_DOMAIN(UNCORE) << 4)|2,
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BOXKEY_PL1_RAM_ON = BOXKEY_PL1_OR | (PWR_DOMAIN(RAM) << 4)|1,
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BOXKEY_PL1_RAM_OFF = BOXKEY_PL1_OR | (PWR_DOMAIN(RAM) << 4)|2,
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BOXKEY_PL1_PLATFORM_ON = BOXKEY_PL1_OR | (PWR_DOMAIN(PLATFORM) << 4)|1,
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BOXKEY_PL1_PLATFORM_OFF = BOXKEY_PL1_OR | (PWR_DOMAIN(PLATFORM) << 4)|2,
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BOXKEY_PL2_PKG_ON = BOXKEY_PL2_OR | (PWR_DOMAIN(PKG) << 4)|1,
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BOXKEY_PL2_PKG_OFF = BOXKEY_PL2_OR | (PWR_DOMAIN(PKG) << 4)|2,
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BOXKEY_PL2_CORES_ON = BOXKEY_PL2_OR | (PWR_DOMAIN(CORES) << 4)|1,
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BOXKEY_PL2_CORES_OFF = BOXKEY_PL2_OR | (PWR_DOMAIN(CORES) << 4)|2,
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BOXKEY_PL2_UNCORE_ON = BOXKEY_PL2_OR | (PWR_DOMAIN(UNCORE) << 4)|1,
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BOXKEY_PL2_UNCORE_OFF = BOXKEY_PL2_OR | (PWR_DOMAIN(UNCORE) << 4)|2,
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BOXKEY_PL2_RAM_ON = BOXKEY_PL2_OR | (PWR_DOMAIN(RAM) << 4)|1,
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BOXKEY_PL2_RAM_OFF = BOXKEY_PL2_OR | (PWR_DOMAIN(RAM) << 4)|2,
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BOXKEY_PL2_PLATFORM_ON = BOXKEY_PL2_OR | (PWR_DOMAIN(PLATFORM) << 4)|1,
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BOXKEY_PL2_PLATFORM_OFF = BOXKEY_PL2_OR | (PWR_DOMAIN(PLATFORM) << 4)|2,
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BOXKEY_TURBO_CLOCK_1C = ((BOXKEY_TURBO_CLOCK_NC | 1) << 32),
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BOXKEY_TURBO_CLOCK_2C = ((BOXKEY_TURBO_CLOCK_NC | 2) << 32),
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BOXKEY_TURBO_CLOCK_3C = ((BOXKEY_TURBO_CLOCK_NC | 3) << 32),
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BOXKEY_TURBO_CLOCK_4C = ((BOXKEY_TURBO_CLOCK_NC | 4) << 32),
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BOXKEY_TURBO_CLOCK_5C = ((BOXKEY_TURBO_CLOCK_NC | 5) << 32),
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BOXKEY_TURBO_CLOCK_6C = ((BOXKEY_TURBO_CLOCK_NC | 6) << 32),
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BOXKEY_TURBO_CLOCK_7C = ((BOXKEY_TURBO_CLOCK_NC | 7) << 32),
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BOXKEY_TURBO_CLOCK_8C = ((BOXKEY_TURBO_CLOCK_NC | 8) << 32),
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BOXKEY_TURBO_CLOCK_9C = ((BOXKEY_TURBO_CLOCK_NC | 9) << 32),
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BOXKEY_TURBO_CLOCK_10C = ((BOXKEY_TURBO_CLOCK_NC | 10) << 32),
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BOXKEY_TURBO_CLOCK_11C = ((BOXKEY_TURBO_CLOCK_NC | 11) << 32),
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BOXKEY_TURBO_CLOCK_12C = ((BOXKEY_TURBO_CLOCK_NC | 12) << 32),
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BOXKEY_TURBO_CLOCK_13C = ((BOXKEY_TURBO_CLOCK_NC | 13) << 32),
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BOXKEY_TURBO_CLOCK_14C = ((BOXKEY_TURBO_CLOCK_NC | 14) << 32),
|
|
BOXKEY_TURBO_CLOCK_15C = ((BOXKEY_TURBO_CLOCK_NC | 15) << 32),
|
|
BOXKEY_TURBO_CLOCK_16C = ((BOXKEY_TURBO_CLOCK_NC | 16) << 32),
|
|
BOXKEY_TURBO_CLOCK_17C = ((BOXKEY_TURBO_CLOCK_NC | 17) << 32),
|
|
BOXKEY_TURBO_CLOCK_18C = ((BOXKEY_TURBO_CLOCK_NC | 18) << 32),
|
|
|
|
BOXKEY_RATIO_CLOCK_TGT = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_TGT) << 32),
|
|
BOXKEY_RATIO_CLOCK_MAX = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MAX) << 32),
|
|
BOXKEY_RATIO_CLOCK_MIN = ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MIN) << 32),
|
|
BOXKEY_RATIO_CLOCK_HWP_TGT =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_TGT)<<32),
|
|
BOXKEY_RATIO_CLOCK_HWP_MAX =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MAX)<<32),
|
|
BOXKEY_RATIO_CLOCK_HWP_MIN =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MIN)<<32),
|
|
|
|
BOXKEY_RATIO_ACTIVATION =((BOXKEY_CFGTDP_CLOCK_OR|CLOCK_MOD_ACT) << 32),
|
|
|
|
BOXKEY_UNCORE_CLOCK_MAX =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MAX) << 32),
|
|
BOXKEY_UNCORE_CLOCK_MIN =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MIN) << 32)
|
|
};
|
|
|
|
#define POWERED(bit) ( (bit) ? (char*) RSC(PRESENT).CODE() \
|
|
: (char*) RSC(MISSING).CODE() )
|
|
|
|
#define ENABLED(bit) ((bit) ? " ON" : "OFF")
|
|
|
|
#define MARGIN_WIDTH 2
|
|
#define MARGIN_HEIGHT 1
|
|
#define INTER_WIDTH 3
|
|
#define INTER_HEIGHT (3 + 1)
|
|
#define LEADING_LEFT (MIN_WIDTH / (MARGIN_WIDTH + (4 * INTER_WIDTH)))
|
|
#define LEADING_TOP 1
|
|
|
|
#define LOAD_LEAD 4
|
|
|
|
typedef struct {
|
|
Coordinate origin;
|
|
CUINT length;
|
|
ATTRIBUTE *attr;
|
|
ASCII *code;
|
|
} LAYER_DECL_ST;
|
|
|
|
#define LayerDeclare(_ID, _len, _col, _row, _var) \
|
|
LAYER_DECL_ST _var = { \
|
|
.origin = { \
|
|
.col = _col, \
|
|
.row = _row \
|
|
}, \
|
|
.length = _len, \
|
|
.attr = RSC(_ID).ATTR(), \
|
|
.code = RSC(_ID).CODE() \
|
|
}
|
|
|
|
typedef char HBCLK[11 + 1];
|
|
|
|
enum DISPOSAL {
|
|
D_MAINVIEW,
|
|
D_DASHBOARD,
|
|
D_ASCIITEST
|
|
};
|
|
|
|
#define DISPOSAL_SIZE (1 + D_ASCIITEST)
|
|
|
|
enum VIEW {
|
|
V_FREQ,
|
|
V_INST,
|
|
V_CYCLES,
|
|
V_CSTATES,
|
|
V_PACKAGE,
|
|
V_TASKS,
|
|
V_INTR,
|
|
V_SENSORS,
|
|
V_VOLTAGE,
|
|
V_ENERGY,
|
|
V_SLICE
|
|
};
|
|
|
|
#define VIEW_SIZE (1 + V_SLICE)
|
|
|
|
typedef void (*DISPOSAL_FUNC)(Layer*);
|
|
|
|
typedef CUINT (*VIEW_FUNC)(Layer*, const unsigned int, CUINT);
|
|
|
|
#define CELL_ARGS Window *win, \
|
|
unsigned long long key, \
|
|
ATTRIBUTE *attrib, \
|
|
ASCII *item
|
|
|
|
typedef TGrid* (*CELL_FUNC)(CELL_ARGS);
|
|
typedef void (*CPU_ITEM_CALLBACK)(unsigned int, ASCII*);
|
|
typedef void (*PKG_ITEM_CALLBACK)(ASCII*);
|
|
typedef void (*UPDATE_CALLBACK)(TGrid*, DATA_TYPE);
|
|
|
|
#define RENDER_OK 0x000
|
|
#define RENDER_KO 0x010
|
|
#define RENDER_OFF 0x100
|
|
|
|
#define RECORDER_DEFAULT 30
|
|
|
|
#define RECORDER_COMPUTE(_recorder, _interval) \
|
|
({ \
|
|
_recorder.Reset = ( (_recorder.Ratios[_recorder.Select] \
|
|
* RECORDER_DEFAULT \
|
|
* 1000) / _interval ); \
|
|
})
|
|
|
|
#define RECORDER_SECONDS(_tick, _interval) \
|
|
((_interval * _tick) / 1000)
|
|
|
|
#if defined(UBENCH) && UBENCH == 1
|
|
#define Draw_uBenchmark(layer) \
|
|
({ \
|
|
if (draw.Flag.uBench) { \
|
|
size_t len = snprintf(Buffer, 20+1, "%llu", UBENCH_METRIC(0)); \
|
|
LayerFillAt( layer, 0, 0, len, Buffer, \
|
|
MakeAttr(MAGENTA, 0, BLACK, 1) ); \
|
|
} \
|
|
})
|
|
#else
|
|
#define Draw_uBenchmark(layer) {}
|
|
#endif /* UBENCH */
|
|
|
|
struct SETTING_ST {
|
|
unsigned int
|
|
fahrCels: 1-0, /* 0:Celsius || 1:Fahrenheit */
|
|
jouleWatt: 2-1, /* 0:Joule || 1:Watt */
|
|
secret : 3-2, /* 0:Show || 1:Hide Secret Data */
|
|
_padding: 32-3;
|
|
};
|
|
|
|
struct RULER_ST {
|
|
double Minimum,
|
|
Maximum,
|
|
Median;
|
|
|
|
unsigned int Top[BOOST(SIZE)],
|
|
Uniq[BOOST(SIZE)],
|
|
Count;
|
|
struct TOPOF {
|
|
unsigned int Top;
|
|
enum RATIO_BOOST Boost;
|
|
} TopOf;
|
|
};
|
|
|
|
struct DRAW_ST {
|
|
struct {
|
|
#ifndef NO_HEADER
|
|
double TopAvg;
|
|
#endif
|
|
#ifndef NO_FOOTER
|
|
unsigned long FreeRAM;
|
|
int TaskCount;
|
|
#endif
|
|
} Cache;
|
|
struct {
|
|
unsigned int
|
|
layout : 1-0 , /* Draw layout */
|
|
clear : 2-1 , /* Clear screen */
|
|
height : 3-2 , /* Valid height */
|
|
width : 4-3 , /* Valid width */
|
|
daemon : 5-4 , /* Draw dynamic */
|
|
taskVal : 6-5 , /* Display task's value */
|
|
avgOrPC : 7-6 , /* C-states average || % pkg states */
|
|
clkOrLd : 8-7 , /* Relative freq. || % load */
|
|
#if defined(UBENCH) && UBENCH == 1
|
|
uBench : 9-8 , /* Display UI micro-benchmark */
|
|
#endif
|
|
_padding: 32-9 ;
|
|
} Flag;
|
|
enum VIEW View;
|
|
enum DISPOSAL Disposal;
|
|
SCREEN_SIZE Size;
|
|
struct {
|
|
CUINT MinHeight;
|
|
CUINT MaxRows;
|
|
CUINT LoadWidth;
|
|
} Area;
|
|
unsigned int iClock,
|
|
cpuScroll,
|
|
Load;
|
|
struct {
|
|
unsigned int Memory;
|
|
} Unit;
|
|
enum SMB_STRING SmbIndex;
|
|
};
|
|
|
|
struct RECORDER_ST {
|
|
int Reset,
|
|
Select,
|
|
Ratios[];
|
|
};
|