mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 04:12:59 +02:00
722 lines
13 KiB
C
722 lines
13 KiB
C
/*
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* CoreFreq
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* Copyright (C) 2015-2023 CYRIL COURTIAT
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* Licenses: GPL2
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*/
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#define OF( _ptr_ , ...) _ptr_ __VA_ARGS__
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#define RO( _ptr_ , ...) OF( _ptr_##_RO , __VA_ARGS__ )
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#define RW( _ptr_ , ...) OF( _ptr_##_RW , __VA_ARGS__ )
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#define SHM_FILENAME_RO "corefreq-ro-shm"
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#define SHM_FILENAME_RW "corefreq-rw-shm"
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#define SIG_RING_MS (500 * 1000000LU)
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#define CHILD_PS_MS (500 * 1000000LU)
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#define CHILD_TH_MS (500 * 1000000LU)
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enum CHIPSET {
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IC_CHIPSET,
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IC_LAKEPORT,
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IC_LAKEPORT_P,
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IC_LAKEPORT_X,
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IC_CALISTOGA,
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IC_BROADWATER,
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IC_CRESTLINE,
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IC_CANTIGA,
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IC_BEARLAKE_Q,
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IC_BEARLAKE_P,
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IC_BEARLAKE_QF,
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IC_BEARLAKE_X,
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IC_INTEL_3200,
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IC_EAGLELAKE_Q,
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IC_EAGLELAKE_P,
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IC_EAGLELAKE_G,
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IC_PINEVIEW,
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IC_CEDARVIEW,
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IC_BAYTRAIL,
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IC_AIRMONT,
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IC_GOLDMONT_PLUS,
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IC_TYLERSBURG,
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IC_IBEXPEAK,
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IC_IBEXPEAK_M,
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IC_COUGARPOINT,
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IC_PATSBURG,
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IC_CAVECREEK,
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IC_WELLSBURG,
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IC_PANTHERPOINT,
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IC_PANTHERPOINT_M,
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IC_LYNXPOINT,
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IC_LYNXPOINT_M,
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IC_WILDCATPOINT,
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IC_WILDCATPOINT_M,
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IC_SUNRISEPOINT,
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IC_UNIONPOINT,
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IC_CANNONPOINT,
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IC_400_SERIES_P,
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IC_400_SERIES_M,
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IC_495,
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IC_H470,
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IC_Z490,
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IC_Q470,
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IC_HM470,
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IC_QM480,
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IC_WM490,
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IC_W480,
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IC_H510,
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IC_B560,
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IC_H570,
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IC_Q570,
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IC_Z590,
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IC_W580,
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IC_H610,
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IC_B660,
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IC_H670,
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IC_Z690,
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IC_Q670,
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IC_W680,
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IC_WM690,
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IC_HM670,
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IC_ADL_PCH_P,
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IC_Z790,
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IC_H770,
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IC_B760,
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IC_MTL_PCH,
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IC_K8,
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IC_ZEN,
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CHIPSETS
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};
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/* Circular buffer */
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#define RING_SIZE 16
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typedef struct
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{
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Bit64 Toggle __attribute__ ((aligned (8)));
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Bit64 OffLine __attribute__ ((aligned (8)));
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unsigned int Boost[BOOST(SIZE)];
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struct
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{
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CPUID_0x00000000 StdFunc;
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CPUID_0x80000000 ExtFunc;
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unsigned int Microcode;
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struct {
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unsigned short int CfgLock : 1-0,
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IORedir : 2-1,
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Unused : 16-2;
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};
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unsigned short int CStateLimit;
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struct {
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unsigned short int CStateInclude; /* Intel */
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unsigned short int CStateBaseAddr; /* Any I/O BAR */
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};
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} Query;
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struct {
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signed int ApicID,
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CoreID,
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ThreadID,
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PackageID;
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union {
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unsigned int ID;
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struct {
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unsigned int Node : 8-0,
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CCX : 16-8,
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CCD : 24-16,
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CMP : 32-24;
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};
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unsigned int Hybrid_ID;
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} Cluster;
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struct {
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unsigned short x2APIC : 8-0,
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_pad : 12-8,
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Ecore : 13-12,
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Pcore : 14-13,
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BSC : 15-14,
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BSP : 16-15;
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} MP;
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struct {
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unsigned int Set,
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Size;
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unsigned short LineSz,
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Part,
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Way;
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struct {
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unsigned short WriteBack: 1-0,
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Inclusive: 2-1,
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_pad16 : 16-2;
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} Feature;
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} Cache[CACHE_MAX_LEVEL];
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} Topology;
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struct {
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unsigned int Limit[SENSOR_LIMITS_DIM];
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struct {
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unsigned int ClockMod : 16-0,
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Extended : 32-16;
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} DutyCycle;
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unsigned int PowerPolicy;
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struct HWP_STRUCT {
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struct {
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unsigned int Highest,
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Guaranteed,
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Most_Efficient,
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Lowest;
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} Capabilities;
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struct {
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unsigned int Minimum_Perf,
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Maximum_Perf,
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Desired_Perf,
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Energy_Pref;
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} Request;
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} HWP;
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} PowerThermal;
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THERMAL_POINT ThermalPoint;
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struct {
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struct {
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double Limit[SENSOR_LIMITS_DIM];
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} Voltage;
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struct {
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double Limit[SENSOR_LIMITS_DIM];
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} Energy;
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struct {
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double Limit[SENSOR_LIMITS_DIM];
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} Power;
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} Sensors;
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struct FLIP_FLOP {
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struct
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{
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unsigned long long
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INST;
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struct {
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unsigned long long
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UCC,
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URC;
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} C0;
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unsigned long long
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C3,
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C6,
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C7,
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TSC,
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C1;
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struct {
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unsigned long long ACCU;
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} Power;
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} Delta __attribute__ ((aligned (8)));
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CLOCK Clock;
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struct {
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double IPS,
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IPC,
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CPI,
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Turbo,
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C0,
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C3,
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C6,
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C7,
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C1,
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Energy,
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Power;
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} State;
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struct {
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double Ratio,
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Freq;
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} Relative;
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struct {
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double Freq;
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struct {
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double Perf; /* STATUS or BOOST P-State */
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} Ratio;
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} Absolute;
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struct {
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unsigned int Sensor,
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Temp;
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enum THERM_PWR_EVENTS Events[eDIM];
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THERMAL_PARAM Param;
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} Thermal;
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struct {
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int VID;
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double Vcore;
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} Voltage;
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struct {
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unsigned int SMI;
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struct {
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unsigned int LOCAL,
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UNKNOWN,
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PCISERR,
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IOCHECK;
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} NMI;
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} Counter;
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} FlipFlop[2];
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struct {
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double Freq[SENSOR_LIMITS_DIM];
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} Relative;
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struct {
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double Freq[SENSOR_LIMITS_DIM];
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} Absolute;
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struct {
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Bit64 RFLAGS __attribute__ ((aligned (8))),
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CR0 __attribute__ ((aligned (8))),
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CR3 __attribute__ ((aligned (8))),
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CR4 __attribute__ ((aligned (8))),
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CR8 __attribute__ ((aligned (8))),
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EFCR __attribute__ ((aligned (8))),
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EFER __attribute__ ((aligned (8))),
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XCR0 __attribute__ ((aligned (8))),
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SYSCFG __attribute__ ((aligned (8)));
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} SystemRegister;
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CPUID_STRUCT CpuID[CPUID_MAX_FUNC];
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struct SLICE_STRUCT {
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struct
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{
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unsigned long long TSC,
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INST;
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} Delta;
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struct {
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unsigned long long TSC,
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INST;
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} Counter[3];
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unsigned long long Error;
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struct {
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struct random_data data;
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char state[128];
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int value[2];
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} Random;
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struct {
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unsigned long long inside,
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trials;
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} Monte_Carlo;
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} Slice __attribute__ ((aligned (8)));
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} CPU_STRUCT;
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typedef struct
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{
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Bit64 Toggle __attribute__ ((aligned (8)));
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FEATURES Features;
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Bit64 PowerNow __attribute__ ((aligned (8)));
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struct {
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unsigned long long
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PowerNow : 1-0,
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ODCM : 2-1,
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PowerMgmt : 3-2,
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EIST : 4-3,
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Turbo : 5-4,
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C1E : 6-5,
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C3A : 7-6,
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C1A : 8-7,
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C3U : 9-8,
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C1U : 10-9,
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CC6 : 11-10,
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PC6 : 12-11,
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SMM : 13-12,
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VM : 14-13,
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IOMMU : 15-14,
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RaceToHalt : 16-15,
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L1_HW_Prefetch : 17-16,
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L1_HW_IP_Prefetch:18-17,
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L2_HW_Prefetch : 19-18,
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L2_HW_CL_Prefetch:20-19,
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IOMMU_Ver_Major : 24-20,
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IOMMU_Ver_Minor : 28-24,
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WDT : 29-28,
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TM1 : 31-29,
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TM2 : 33-31,
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L1_Scrubbing : 34-33,
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_pad64 : 64-34;
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} Technology;
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struct {
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unsigned long long
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IBRS : 2-0,
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STIBP : 4-2,
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SSBD : 6-4,
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RDCL_NO : 8-6,
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IBRS_ALL : 10-8,
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RSBA : 12-10,
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L1DFL_VMENTRY_NO: 14-12,
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SSB_NO : 16-14,
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MDS_NO : 18-16,
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PSCHANGE_MC_NO : 20-18,
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TAA_NO : 22-20,
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STLB : 24-22,
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FUSA : 26-24,
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RSM_CPL0 : 28-26,
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SPLA : 30-28,
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SNOOP_FILTER : 32-30,
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PSFD : 34-32,
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DOITM_EN : 36-34,
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SBDR_SSDP_NO : 38-36,
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FBSDP_NO : 40-38,
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PSDP_NO : 42-40,
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FB_CLEAR : 44-42,
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SRBDS : 45-44,
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RNGDS : 47-45,
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RTM : 49-47,
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VERW : 51-49,
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RRSBA : 53-51,
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BHI_NO : 55-53,
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XAPIC_DIS : 57-55,
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PBRSB_NO : 59-57,
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IPRED_DIS_U : 61-59,
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IPRED_DIS_S : 63-61,
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MCDT_NO : 64-63,
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RRSBA_DIS_U : 2-0,
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RRSBA_DIS_S : 4-2,
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BHI_DIS_S : 6-4,
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BTC_NOBR : 8-6,
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DRAM_Scrambler : 10-8,
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TSME : 12-10,
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DDPD_U_DIS : 14-12,
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_UnusedMechBits : 64-14;
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} Mechanisms;
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enum THERMAL_FORMULAS thermalFormula;
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enum VOLTAGE_FORMULAS voltageFormula;
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enum POWER_FORMULAS powerFormula;
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struct {
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unsigned int Count,
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OnLine;
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} CPU;
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SERVICE_PROC Service;
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unsigned int PM_version;
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struct {
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unsigned int Rel,
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Abs;
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} Top;
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struct PKG_FLIP_FLOP {
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struct {
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unsigned long long PCLK;
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union {
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struct {
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unsigned long long PC02,
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PC03,
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PC04,
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PC06,
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PC07,
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PC08,
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PC09,
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PC10;
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};
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#if defined(ARCH_PMC)
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unsigned long long
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CTR[MC_VECTOR_TO_SCALAR(MC_MAX_CTRL, MC_MAX_CHA)];
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#endif
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};
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unsigned long long MC6,
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ACCU[PWR_DOMAIN(SIZE)];
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} Delta;
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struct {
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unsigned long long FC0;
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} Uncore;
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struct {
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unsigned int Sensor,
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Temp;
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enum THERM_PWR_EVENTS Events[eDIM];
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} Thermal;
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struct {
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struct {
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int CPU, SOC;
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} VID;
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double CPU, SOC;
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} Voltage;
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} FlipFlop[2] __attribute__ ((aligned (8)));
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struct {
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double PC02,
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PC03,
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PC04,
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PC06,
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PC07,
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PC08,
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PC09,
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PC10,
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MC6;
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struct {
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double Limit[SENSOR_LIMITS_DIM];
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} Voltage;
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struct {
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double Current,
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Limit[SENSOR_LIMITS_DIM];
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} Energy[PWR_DOMAIN(SIZE)];
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struct {
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double Current,
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Limit[SENSOR_LIMITS_DIM];
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} Power[PWR_DOMAIN(SIZE)];
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} State;
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struct {
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double Turbo,
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C0,
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C3,
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C6,
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C7,
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C1,
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MC6;
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} Avg;
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struct {
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struct {
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double Watts,
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Joules,
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Times;
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} Unit;
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struct {
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double TAU[PWR_LIMIT_SIZE];
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unsigned short PWL[PWR_LIMIT_SIZE];
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struct {
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unsigned char Enable : 1-0,
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Clamping: 2-1,
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Unlock : 3-2,
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_Unused : 8-3;
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union {
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unsigned char TW;
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struct {
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unsigned char TW_Y : 5-0,
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TW_Z : 7-5,
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MaskBit : 8-7;
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};
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};
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} Feature[PWR_LIMIT_SIZE];
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} Domain[PWR_DOMAIN(SIZE)];
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unsigned short TDP, Min, Max;
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unsigned short PPT, EDC, TDC;
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struct {
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unsigned short TDC : 1-0,
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_Unused : 16-1;
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} Feature;
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} Power;
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THERMAL_POINT ThermalPoint;
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signed int ArchID;
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enum HYPERVISOR HypervisorID;
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char Architecture[CODENAME_LEN],
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Brand[BRAND_SIZE];
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} PROC_STRUCT;
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typedef struct
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{
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FOOTPRINT FootPrint;
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BitCC roomSched __attribute__ ((aligned (16)));
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enum THERM_PWR_EVENTS ProcessorEvents[eDIM];
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struct { /* NMI bits: 0 is Unregistered; 1 is Registered */
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Bit64 NMI __attribute__ ((aligned (8)));
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signed int AutoClock, /* 10: Auto, 01: Init, 00: Specs */
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Experimental,/* 0: Disable, 1: Enable */
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HotPlug, /* < 0: Disable, Other: Enable */
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PCI; /* < 0: Disable, other: Enable */
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struct { /* = 0: Disable, 1: Enable */
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unsigned int HSMP : 1-0,
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_pad32 : 32-1;
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};
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KERNEL_DRIVER Driver; /*0:Disable, 1:Enable, 2:Full-control*/
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} Registration;
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struct {
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Bit64 Operation __attribute__ ((aligned (8)));
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OS_DRIVER OS;
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unsigned int tickReset,
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tickStep;
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pid_t trackTask;
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enum SORTBYFIELD sortByField;
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int reverseOrder,
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taskCount;
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TASK_MCB taskList[TASK_LIMIT];
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MEM_MCB memInfo;
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struct {
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unsigned short version,
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major,
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minor;
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} kernel;
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unsigned short procCount;
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char sysname[MAX_UTS_LEN],
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release[MAX_UTS_LEN],
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version[MAX_UTS_LEN],
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machine[MAX_UTS_LEN];
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} SysGate;
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struct {
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unsigned char index[8];
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char array[MAX_UTS_LEN];
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} CS;
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|
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struct {
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unsigned int Interval;
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struct timespec pollingWait,
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ringWaiting,
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childWaiting,
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sliceWaiting;
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} Sleep;
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time_t StartedAt;
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char ShmName[TASK_COMM_LEN];
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struct {
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pid_t Svr,
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Cli,
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GUI;
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} App;
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|
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struct {
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unsigned int Boost[UNCORE_BOOST(SIZE)];
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struct
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{
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unsigned long long Speed;
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unsigned int Rate;
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} Bus;
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|
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struct {
|
|
struct {
|
|
RAM_TIMING Timing;
|
|
RAM_GEOMETRY DIMM[MC_MAX_DIMM];
|
|
} Channel[MC_MAX_CHA];
|
|
unsigned short SlotCount, ChannelCount;
|
|
} MC[MC_MAX_CTRL];
|
|
|
|
unsigned long long CtrlSpeed;
|
|
unsigned short CtrlCount,
|
|
ChipID;
|
|
|
|
struct {
|
|
unsigned short /* 00:MHz , 01:MT/s , 10:MB/s , 11:VOID */
|
|
Bus_Rate: 2-0,
|
|
BusSpeed: 4-2,
|
|
DDR_Rate: 6-4,
|
|
DDRSpeed: 8-6,
|
|
DDR_Std : 12-8,
|
|
DDR_Ver : 16-12;
|
|
} Unit;
|
|
|
|
struct {
|
|
enum CHIPSET ArchID;
|
|
char CodeName[CODENAME_LEN];
|
|
} Chipset;
|
|
} Uncore;
|
|
|
|
SMBIOS_ST SMB;
|
|
|
|
PROC_STRUCT Proc;
|
|
CPU_STRUCT Cpu[];
|
|
} SHM_STRUCT_RO;
|
|
|
|
typedef struct {
|
|
struct {
|
|
Bit64 Sync __attribute__ ((aligned (8)));
|
|
} Proc;
|
|
|
|
struct {
|
|
RING_CTRL buffer[RING_SIZE] __attribute__((aligned(16)));
|
|
unsigned int head, tail;
|
|
} Ring[2]; /* [0] Parent ; [1] Child */
|
|
|
|
struct {
|
|
RING_CTRL buffer[RING_SIZE] __attribute__((aligned(16)));
|
|
unsigned int head, tail;
|
|
} Error;
|
|
} SHM_STRUCT_RW;
|
|
|
|
/* Error Reasons management. */
|
|
typedef struct {
|
|
__typeof__ (errno) no: 32;
|
|
__typeof__ (__LINE__) ln: 26;
|
|
enum REASON_CLASS rc: 6;
|
|
} REASON_CODE;
|
|
|
|
#define REASON_SET_2xARG(_reason, _rc, _no) \
|
|
{ \
|
|
_reason.no = _no; \
|
|
_reason.ln = __LINE__; \
|
|
_reason.rc = _rc; \
|
|
}
|
|
|
|
#define REASON_SET_1xARG(_reason, _rc) \
|
|
{ \
|
|
_reason.no = errno; \
|
|
_reason.ln = __LINE__; \
|
|
_reason.rc = _rc; \
|
|
}
|
|
|
|
#define REASON_SET_0xARG(_reason) \
|
|
{ \
|
|
_reason.no = errno; \
|
|
_reason.ln = __LINE__; \
|
|
_reason.rc = RC_SYS_CALL; \
|
|
}
|
|
|
|
#define REASON_DISPATCH(_1,_2,_3,REASON_CURSOR, ... ) REASON_CURSOR
|
|
|
|
#define REASON_SET( ... ) \
|
|
REASON_DISPATCH( __VA_ARGS__ , REASON_SET_2xARG, \
|
|
REASON_SET_1xARG, \
|
|
REASON_SET_0xARG)( __VA_ARGS__ )
|
|
|
|
#define REASON_INIT(_reason) \
|
|
REASON_CODE _reason = {.no = 0, .ln = 0, .rc = RC_SUCCESS}
|
|
|
|
#define IS_REASON_SUCCESSFUL(_reason) (_reason.rc == RC_SUCCESS)
|
|
|
|
#if defined(UBENCH) && UBENCH == 1
|
|
#define Print_uBenchmark(quiet) \
|
|
({ \
|
|
if (quiet) \
|
|
printf("%llu\t%llu\n",UBENCH_METRIC(0),UBENCH_METRIC(1));\
|
|
})
|
|
#else
|
|
#define Print_uBenchmark(quiet) {}
|
|
#endif /* UBENCH */
|
|
|
|
#define ELAPSED(ref) \
|
|
({ \
|
|
time_t now; \
|
|
time(&now); \
|
|
now - ref; \
|
|
})
|