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[Intel] Added method CLOCK_FLEX_MAX with Xeon's Nehalem & Core 2

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* Grants full `MSR_FLEX_RATIO` access to tested architectures:
- Alder Lake/S
- Tiger Lake/U
- Westmere/Gulftown
This commit is contained in:
CyrIng
2024-06-02 16:40:40 +02:00
parent db15a83fb8
commit f622261545
7 changed files with 122 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
x86_64/corefreq-cli-rsc-en.h
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@@ -855,6 +855,7 @@
#define RSC_RATIO_CODE_EN "Ratio" #define RSC_RATIO_CODE_EN "Ratio"
#define RSC_FACTORY_CODE_EN "Factory" #define RSC_FACTORY_CODE_EN "Factory"
#define RSC_OVERCLOCK_CODE_EN "Overclock" #define RSC_OVERCLOCK_CODE_EN "Overclock"
#define RSC_OC_BINS_COMM_CODE_EN " OC_BINS [0:disabled ... 7:unlimited] "
#define RSC_PERFORMANCE_CODE_EN "Performance" #define RSC_PERFORMANCE_CODE_EN "Performance"
#define RSC_TARGET_CODE_EN "Target" #define RSC_TARGET_CODE_EN "Target"
#define RSC_LEVEL_CODE_EN "Level" #define RSC_LEVEL_CODE_EN "Level"
@@ -1261,6 +1262,7 @@
#define RSC_TECH_INTEL_VTD_COMM_CODE_EN " I/O MMU virtualization (Intel VT-d) " #define RSC_TECH_INTEL_VTD_COMM_CODE_EN " I/O MMU virtualization (Intel VT-d) "
#define RSC_TECH_AMD_V_COMM_CODE_EN " I/O MMU virtualization (AMD-Vi) " #define RSC_TECH_AMD_V_COMM_CODE_EN " I/O MMU virtualization (AMD-Vi) "
#define RSC_TECH_HDCP_COMM_CODE_EN " High-Bandwidth Digital Content Protection " #define RSC_TECH_HDCP_COMM_CODE_EN " High-Bandwidth Digital Content Protection "
#define RSC_TECH_OC_COMM_CODE_EN " If OC_ENABLED then MSR FLEX_RATIO.OC_BINS "
#define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring " #define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring "
#define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities " #define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities "

4
x86_64/corefreq-cli-rsc-fr.h
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@@ -358,6 +358,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_RATIO_CODE_FR "Ratio" #define RSC_RATIO_CODE_FR "Ratio"
#define RSC_FACTORY_CODE_FR "Usine" #define RSC_FACTORY_CODE_FR "Usine"
#define RSC_OVERCLOCK_CODE_FR "Overclock" #define RSC_OVERCLOCK_CODE_FR "Overclock"
#define RSC_OC_BINS_COMM_CODE_FR \
" OC_BINS [0:d""\xa9""sactiv""\xa9"" ... 7:illimit""\xa9""] "
#define RSC_PERFORMANCE_CODE_FR "Performance" #define RSC_PERFORMANCE_CODE_FR "Performance"
#define RSC_TARGET_CODE_FR "Cible" #define RSC_TARGET_CODE_FR "Cible"
#define RSC_LEVEL_CODE_FR "Niveau" #define RSC_LEVEL_CODE_FR "Niveau"
@@ -741,6 +744,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_TECH_INTEL_VTD_COMM_CODE_FR RSC_TECH_INTEL_VTD_COMM_CODE_EN #define RSC_TECH_INTEL_VTD_COMM_CODE_FR RSC_TECH_INTEL_VTD_COMM_CODE_EN
#define RSC_TECH_AMD_V_COMM_CODE_FR RSC_TECH_AMD_V_COMM_CODE_EN #define RSC_TECH_AMD_V_COMM_CODE_FR RSC_TECH_AMD_V_COMM_CODE_EN
#define RSC_TECH_HDCP_COMM_CODE_FR RSC_TECH_HDCP_COMM_CODE_EN #define RSC_TECH_HDCP_COMM_CODE_FR RSC_TECH_HDCP_COMM_CODE_EN
#define RSC_TECH_OC_COMM_CODE_FR " Si OC_ENABLED alors MSR FLEX_RATIO.OC_BINS "
#define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance " #define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance "
#define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances " #define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances "

2
x86_64/corefreq-cli-rsc.c
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@@ -554,6 +554,7 @@ RESOURCE_ST Resource[] = {
LDT(RSC_RATIO), LDT(RSC_RATIO),
LDT(RSC_FACTORY), LDT(RSC_FACTORY),
LDT(RSC_OVERCLOCK), LDT(RSC_OVERCLOCK),
LDT(RSC_OC_BINS_COMM),
LDT(RSC_PERFORMANCE), LDT(RSC_PERFORMANCE),
LDT(RSC_TARGET), LDT(RSC_TARGET),
LDT(RSC_LEVEL), LDT(RSC_LEVEL),
@@ -1160,6 +1161,7 @@ RESOURCE_ST Resource[] = {
LDT(RSC_TECHNOLOGIES_IPU), LDT(RSC_TECHNOLOGIES_IPU),
LDT(RSC_TECHNOLOGIES_VPU), LDT(RSC_TECHNOLOGIES_VPU),
LDT(RSC_TECHNOLOGIES_OC), LDT(RSC_TECHNOLOGIES_OC),
LDT(RSC_TECH_OC_COMM),
LDT(RSC_PERF_MON_TITLE), LDT(RSC_PERF_MON_TITLE),
LDT(RSC_PERF_CAPS_TITLE), LDT(RSC_PERF_CAPS_TITLE),
LDT(RSC_VERSION), LDT(RSC_VERSION),

2
x86_64/corefreq-cli-rsc.h
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@@ -357,6 +357,7 @@ enum {
RSC_RATIO, RSC_RATIO,
RSC_FACTORY, RSC_FACTORY,
RSC_OVERCLOCK, RSC_OVERCLOCK,
RSC_OC_BINS_COMM,
RSC_PERFORMANCE, RSC_PERFORMANCE,
RSC_TARGET, RSC_TARGET,
RSC_LEVEL, RSC_LEVEL,
@@ -963,6 +964,7 @@ enum {
RSC_TECHNOLOGIES_IPU, RSC_TECHNOLOGIES_IPU,
RSC_TECHNOLOGIES_VPU, RSC_TECHNOLOGIES_VPU,
RSC_TECHNOLOGIES_OC, RSC_TECHNOLOGIES_OC,
RSC_TECH_OC_COMM,
RSC_PERF_MON_TITLE, RSC_PERF_MON_TITLE,
RSC_PERF_CAPS_TITLE, RSC_PERF_CAPS_TITLE,
RSC_VERSION, RSC_VERSION,

13
x86_64/corefreq-cli.c
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@@ -1357,11 +1357,12 @@ REASON_CODE SysInfoProc(Window *win,
RO(Shm)->Proc.Features.OC_Lock ? RO(Shm)->Proc.Features.OC_Lock ?
RSC(LOCK).CODE() : RSC(UNLOCK).CODE() ); RSC(LOCK).CODE() : RSC(UNLOCK).CODE() );
PUT( SCANKEY_NULL, attrib[3], width, 0, GridHover( PUT( SCANKEY_NULL, attrib[3], width, 0,
"%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]", "%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]",
17, hSpace, RSC(BIN).CODE(), 17, hSpace, RSC(BIN).CODE(),
2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock, 2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock,
23, hSpace, RO(Shm)->Proc.Features.Factory.Bins ); 23, hSpace, RO(Shm)->Proc.Features.Factory.Bins ),
(char *) RSC(OC_BINS_COMM).CODE() );
} }
PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE()); PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE());
@@ -4458,7 +4459,7 @@ REASON_CODE SysInfoTech(Window *win,
(unsigned int[]) { CRC_INTEL, 0 }, (unsigned int[]) { CRC_INTEL, 0 },
RO(Shm)->Proc.Technology.OC == 1, RO(Shm)->Proc.Technology.OC == 1,
2, "%s%.*sOC [%3s]", 2, "%s%.*sOC [%3s]",
RSC(TECHNOLOGIES_OC).CODE(), NULL, RSC(TECHNOLOGIES_OC).CODE(), RSC(TECH_OC_COMM).CODE(),
width - 13 - RSZ(TECHNOLOGIES_OC), width - 13 - RSZ(TECHNOLOGIES_OC),
NULL, NULL,
SCANKEY_NULL, SCANKEY_NULL,

193
x86_64/corefreqk.c
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@@ -2687,104 +2687,105 @@ static void Intel_FlexRatio(bool OC_ENABLED)
struct SIGNATURE Arch; struct SIGNATURE Arch;
unsigned short grantFlex : 1-0, unsigned short grantFlex : 1-0,
experimental : 2-1, experimental : 2-1,
freeToUse : 16-2; freeToUse : 8-2,
bitsLayout : 16-8;
} list[] = { } list[] = {
{_Core_Yonah, 0, 1, 0}, {_Core_Yonah, 0, 1, 0, 1},
{_Core_Conroe, 0, 1, 0}, {_Core_Conroe, 0, 1, 0, 1},
{_Core_Kentsfield, 0, 1, 0}, {_Core_Kentsfield, 0, 1, 0, 1},
{_Core_Conroe_616, 0, 1, 0}, {_Core_Conroe_616, 0, 1, 0, 1},
{_Core_Penryn, 0, 1, 0}, {_Core_Penryn, 1, 1, 0, 1}, /* 06_17 */
{_Core_Dunnington, 0, 1, 0}, {_Core_Dunnington, 0, 1, 0, 1},
{_Atom_Bonnell, 0, 1, 0}, /* 06_1C */ {_Atom_Bonnell, 0, 1, 0, 0}, /* 06_1C */
{_Atom_Silvermont, 0, 1, 0}, /* 06_26 */ {_Atom_Silvermont, 0, 1, 0, 0}, /* 06_26 */
{_Atom_Lincroft, 0, 1, 0}, /* 06_27 */ {_Atom_Lincroft, 0, 1, 0, 0}, /* 06_27 */
{_Atom_Clover_Trail, 0, 1, 0}, /* 06_35 */ {_Atom_Clover_Trail, 0, 1, 0, 0}, /* 06_35 */
{_Atom_Saltwell, 0, 1, 0}, /* 06_36 */ {_Atom_Saltwell, 0, 1, 0, 0}, /* 06_36 */
{_Silvermont_Bay_Trail, 0, 1, 0}, /* 06_37 */ {_Silvermont_Bay_Trail, 0, 1, 0, 0}, /* 06_37 */
{_Atom_Avoton, 0, 1, 0}, /* 06_4D */ {_Atom_Avoton, 0, 1, 0, 0}, /* 06_4D */
{_Atom_Airmont, 0, 1, 0}, /* 06_4C */ {_Atom_Airmont, 0, 1, 0, 0}, /* 06_4C */
{_Atom_Goldmont, 1, 1, 0}, /* 06_5C */ {_Atom_Goldmont, 1, 1, 0, 0}, /* 06_5C */
{_Atom_Sofia, 1, 1, 0}, /* 06_5D */ {_Atom_Sofia, 1, 1, 0, 0}, /* 06_5D */
{_Atom_Merrifield, 1, 1, 0}, /* 06_4A */ {_Atom_Merrifield, 1, 1, 0, 0}, /* 06_4A */
{_Atom_Moorefield, 1, 1, 0}, /* 06_5A */ {_Atom_Moorefield, 1, 1, 0, 0}, /* 06_5A */
{_Nehalem_Bloomfield, 1, 1, 0}, /* 06_1A */ {_Nehalem_Bloomfield, 1, 1, 0, 1}, /* 06_1A */
{_Nehalem_Lynnfield, 1, 1, 0}, /* 06_1E */ {_Nehalem_Lynnfield, 1, 1, 0, 1}, /* 06_1E */
{_Nehalem_MB, 1, 1, 0}, /* 06_1F */ {_Nehalem_MB, 1, 1, 0, 1}, /* 06_1F */
{_Nehalem_EX, 1, 1, 0}, /* 06_2E */ {_Nehalem_EX, 1, 1, 0, 1}, /* 06_2E */
{_Westmere, 1, 1, 0}, /* 06_25 */ {_Westmere, 1, 1, 0, 1}, /* 06_25 */
{_Westmere_EP, 1, 1, 0}, /* 06_2C */ {_Westmere_EP, 1, 0, 0, 1}, /* 06_2C */
{_Westmere_EX, 1, 1, 0}, /* 06_2F */ {_Westmere_EX, 1, 1, 0, 1}, /* 06_2F */
{_SandyBridge, 1, 1, 0}, /* 06_2A */ {_SandyBridge, 1, 1, 0, 0}, /* 06_2A */
{_SandyBridge_EP, 1, 1, 0}, /* 06_2D */ {_SandyBridge_EP, 1, 1, 0, 0}, /* 06_2D */
{_IvyBridge, 1, 0, 0}, /* 06_3A */ {_IvyBridge, 1, 0, 0, 0}, /* 06_3A */
{_IvyBridge_EP, 1, 1, 0}, /* 06_3E */ {_IvyBridge_EP, 1, 1, 0, 0}, /* 06_3E */
{_Haswell_DT, 1, 1, 0}, /* 06_3C */ {_Haswell_DT, 1, 1, 0, 0}, /* 06_3C */
{_Haswell_EP, 1, 1, 0}, /* 06_3F */ {_Haswell_EP, 1, 1, 0, 0}, /* 06_3F */
{_Haswell_ULT, 1, 1, 0}, /* 06_45 */ {_Haswell_ULT, 1, 1, 0, 0}, /* 06_45 */
{_Haswell_ULX, 1, 1, 0}, /* 06_46 */ {_Haswell_ULX, 1, 1, 0, 0}, /* 06_46 */
{_Broadwell, 1, 1, 0}, /* 06_3D */ {_Broadwell, 1, 1, 0, 0}, /* 06_3D */
{_Broadwell_D, 1, 1, 0}, /* 06_56 */ {_Broadwell_D, 1, 1, 0, 0}, /* 06_56 */
{_Broadwell_H, 1, 1, 0}, /* 06_47 */ {_Broadwell_H, 1, 1, 0, 0}, /* 06_47 */
{_Broadwell_EP, 1, 1, 0}, /* 06_4F */ {_Broadwell_EP, 1, 1, 0, 0}, /* 06_4F */
{_Skylake_UY, 1, 1, 0}, /* 06_4E */ {_Skylake_UY, 1, 1, 0, 0}, /* 06_4E */
{_Skylake_S, 1, 1, 0}, /* 06_5E */ {_Skylake_S, 1, 1, 0, 0}, /* 06_5E */
{_Skylake_X, 1, 1, 0}, /* 06_55 */ {_Skylake_X, 1, 1, 0, 0}, /* 06_55 */
{_Xeon_Phi, 0, 1, 0}, /* 06_57 */ {_Xeon_Phi, 0, 1, 0, 0}, /* 06_57 */
{_Kabylake, 1, 1, 0}, /* 06_9E */ {_Kabylake, 1, 1, 0, 0}, /* 06_9E */
{_Kabylake_UY, 1, 1, 0}, /* 06_8E */ {_Kabylake_UY, 1, 1, 0, 0}, /* 06_8E */
{_Cannonlake_U, 1, 1, 0}, /* 06_66 */ {_Cannonlake_U, 1, 1, 0, 0}, /* 06_66 */
{_Cannonlake_H, 1, 1, 0}, {_Cannonlake_H, 1, 1, 0, 0},
{_Geminilake, 1, 1, 0}, /* 06_7A */ {_Geminilake, 1, 1, 0, 0}, /* 06_7A */
{_Icelake_UY, 1, 1, 0}, /* 06_7E */ {_Icelake_UY, 1, 1, 0, 0}, /* 06_7E */
{_Icelake_X, 1, 1, 0}, {_Icelake_X, 1, 1, 0, 0},
{_Icelake_D, 1, 1, 0}, {_Icelake_D, 1, 1, 0, 0},
{_Sunny_Cove, 1, 1, 0}, {_Sunny_Cove, 1, 1, 0, 0},
{_Tigerlake, 1, 1, 0}, {_Tigerlake, 1, 1, 0, 0},
{_Tigerlake_U, 1, 1, 0}, /* 06_8C */ {_Tigerlake_U, 1, 0, 0, 0}, /* 06_8C */
{_Cometlake, 1, 1, 0}, {_Cometlake, 1, 1, 0, 0},
{_Cometlake_UY, 1, 1, 0}, {_Cometlake_UY, 1, 1, 0, 0},
{_Atom_Denverton, 1, 1, 0}, {_Atom_Denverton, 1, 1, 0, 0},
{_Tremont_Jacobsville, 1, 1, 0}, {_Tremont_Jacobsville, 1, 1, 0, 0},
{_Tremont_Lakefield, 1, 1, 0}, {_Tremont_Lakefield, 1, 1, 0, 0},
{_Tremont_Elkhartlake, 1, 1, 0}, {_Tremont_Elkhartlake, 1, 1, 0, 0},
{_Tremont_Jasperlake, 1, 1, 0}, {_Tremont_Jasperlake, 1, 1, 0, 0},
{_Sapphire_Rapids, 1, 1, 0}, {_Sapphire_Rapids, 1, 1, 0, 0},
{_Emerald_Rapids, 1, 1, 0}, {_Emerald_Rapids, 1, 1, 0, 0},
{_Granite_Rapids_X, 1, 1, 0}, {_Granite_Rapids_X, 1, 1, 0, 0},
{_Granite_Rapids_D, 1, 1, 0}, {_Granite_Rapids_D, 1, 1, 0, 0},
{_Sierra_Forest, 1, 1, 0}, {_Sierra_Forest, 1, 1, 0, 0},
{_Grand_Ridge, 1, 1, 0}, {_Grand_Ridge, 1, 1, 0, 0},
{_Rocketlake, 1, 1, 0}, {_Rocketlake, 1, 1, 0, 0},
{_Rocketlake_U, 1, 1, 0}, {_Rocketlake_U, 1, 1, 0, 0},
{_Alderlake_S, 1, 1, 0}, /* 06_97 */ {_Alderlake_S, 1, 0, 0, 0}, /* 06_97 */
{_Alderlake_H, 1, 1, 0}, {_Alderlake_H, 1, 1, 0, 0},
{_Alderlake_N, 1, 1, 0}, {_Alderlake_N, 1, 1, 0, 0},
{_Meteorlake_M, 1, 1, 0}, {_Meteorlake_M, 1, 1, 0, 0},
{_Meteorlake_N, 1, 1, 0}, {_Meteorlake_N, 1, 1, 0, 0},
{_Meteorlake_S, 1, 1, 0}, {_Meteorlake_S, 1, 1, 0, 0},
{_Raptorlake, 1, 1, 0}, /* 06_B7 */ {_Raptorlake, 1, 1, 0, 0}, /* 06_B7 */
{_Raptorlake_P, 1, 1, 0}, {_Raptorlake_P, 1, 1, 0, 0},
{_Raptorlake_S, 1, 1, 0}, {_Raptorlake_S, 1, 1, 0, 0},
{_Lunarlake, 1, 1, 0}, /* 06_BD */ {_Lunarlake, 1, 1, 0, 0}, /* 06_BD */
{_Arrowlake, 1, 1, 0}, /* 06_C6 */ {_Arrowlake, 1, 1, 0, 0}, /* 06_C6 */
{_Arrowlake_H, 1, 1, 0}, /* 06_C5 */ {_Arrowlake_H, 1, 1, 0, 0}, /* 06_C5 */
{_Arrowlake_U, 1, 1, 0}, /* 06_B5 */ {_Arrowlake_U, 1, 1, 0, 0}, /* 06_B5 */
{_Pantherlake, 1, 1, 0}, /* 06_CC */ {_Pantherlake, 1, 1, 0, 0}, /* 06_CC */
{_Clearwater_Forest, 1, 1, 0} /* 06_DD */ {_Clearwater_Forest, 1, 1, 0, 0} /* 06_DD */
}; };
const unsigned int ids = sizeof(list) / sizeof(list[0]); const unsigned int ids = sizeof(list) / sizeof(list[0]);
unsigned int id; unsigned int id;
@@ -2798,17 +2799,27 @@ static void Intel_FlexRatio(bool OC_ENABLED)
if (!list[id].experimental if (!list[id].experimental
|| (list[id].experimental || (list[id].experimental
&& PUBLIC(RO(Proc))->Registration.Experimental)) && PUBLIC(RO(Proc))->Registration.Experimental))
{ {
FLEX_RATIO flexRegister = {.value = 0}; FLEX_RATIO flexReg = {.value = 0};
RDMSR(flexRegister, MSR_FLEX_RATIO); RDMSR(flexReg, MSR_FLEX_RATIO);
PUBLIC(RO(Proc))->Features.OC_Enable = flexRegister.OC_ENABLED;
PUBLIC(RO(Proc))->Features.Factory.Bins = flexRegister.OC_BINS; switch (list[id].bitsLayout) {
PUBLIC(RO(Proc))->Features.OC_Lock = flexRegister.OC_LOCK; default:
case 0:
PUBLIC(RO(Proc))->Features.OC_Enable = flexReg.OC_ENABLED;
PUBLIC(RO(Proc))->Features.Factory.Bins = flexReg.OC_BINS;
PUBLIC(RO(Proc))->Features.OC_Lock = flexReg.OC_LOCK;
break;
case 1:
PUBLIC(RO(Proc))->Features.OC_Enable = flexReg.OC_ENABLED;
PUBLIC(RO(Proc))->Features.Factory.Bins=flexReg.CLOCK_FLEX_MAX;
break;
}
PUBLIC(RO(Proc))->Features.Factory.Overclock = \ PUBLIC(RO(Proc))->Features.Factory.Overclock = \
ABS_FREQ_MHz( signed int, ABS_FREQ_MHz( signed int,
PUBLIC(RO(Proc))->Features.Factory.Bins, PUBLIC(RO(Proc))->Features.Factory.Bins,
PUBLIC(RO(Proc))->Features.Factory.Clock ); PUBLIC(RO(Proc))->Features.Factory.Clock );
} }
} }
break; break;
} }
@@ -5993,6 +6004,8 @@ static PCI_CALLBACK X58_QPI(struct pci_dev *dev)
pci_read_config_dword(dev, 0xd0, pci_read_config_dword(dev, 0xd0,
&PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.value); &PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.value);
Intel_FlexRatio(true);
return (PCI_CALLBACK) 0; return (PCI_CALLBACK) 0;
} }

3
x86_64/intel_reg.h
View File

@@ -672,7 +672,8 @@ typedef union
{ /* OC Ratio = BCLK ratio + OC_BINS */ { /* OC Ratio = BCLK ratio + OC_BINS */
unsigned long long unsigned long long
OC_VID : 8-0, OC_VID : 8-0,
UnknownBits1 : 16-8, CLOCK_FLEX_MAX : 12-8, /* R/W: Westmere/Gulftown; Wolfdale */
UnknownBits1 : 16-12,
OC_ENABLED : 17-16, OC_ENABLED : 17-16,
OC_BINS : 20-17, /* 0:Disabled ... 7:Unlimited */ OC_BINS : 20-17, /* 0:Disabled ... 7:Unlimited */
OC_LOCK : 21-20, OC_LOCK : 21-20,