diff --git a/aarch64/corefreqk.h b/aarch64/corefreqk.h index d224ec3..3215f18 100644 --- a/aarch64/corefreqk.h +++ b/aarch64/corefreqk.h @@ -554,10 +554,12 @@ static void Query_DynamIQ(unsigned int cpu) ; static void Query_DynamIQ_CMN(unsigned int cpu) ; /* [Void] */ #define _Void_Signature {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A320 {.ExtFamily=0xd8, .Family=0xf, .ExtModel=0x0, .Model=0x0} #define _Cortex_A34 {.ExtFamily=0xd0, .Family=0x2, .ExtModel=0x0, .Model=0x8} #define _Cortex_A35 {.ExtFamily=0xd0, .Family=0x4, .ExtModel=0x0, .Model=0xa} #define _Cortex_A510 {.ExtFamily=0xd4, .Family=0x6, .ExtModel=0x0, .Model=0x0} #define _Cortex_A520 {.ExtFamily=0xd8, .Family=0x0, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A520AE {.ExtFamily=0xd8, .Family=0x8, .ExtModel=0x0, .Model=0x0} #define _Cortex_A53 {.ExtFamily=0xd0, .Family=0x3, .ExtModel=0x0, .Model=0x3} #define _Cortex_A55 {.ExtFamily=0xd0, .Family=0x5, .ExtModel=0x4, .Model=0x5} #define _Cortex_A57 {.ExtFamily=0xd0, .Family=0x7, .ExtModel=0x0, .Model=0x1} @@ -567,6 +569,8 @@ static void Query_DynamIQ_CMN(unsigned int cpu) ; #define _Cortex_A715 {.ExtFamily=0xd4, .Family=0xd, .ExtModel=0x0, .Model=0x0} #define _Cortex_A72 {.ExtFamily=0xd0, .Family=0x8, .ExtModel=0x0, .Model=0x2} #define _Cortex_A720 {.ExtFamily=0xd8, .Family=0x1, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A720AE {.ExtFamily=0xd8, .Family=0x9, .ExtModel=0x0, .Model=0x0} +#define _Cortex_A725 {.ExtFamily=0xd8, .Family=0x7, .ExtModel=0x0, .Model=0x0} #define _Cortex_A73 {.ExtFamily=0xd0, .Family=0x9, .ExtModel=0x0, .Model=0x4} #define _Cortex_A75 {.ExtFamily=0xd0, .Family=0xa, .ExtModel=0x4, .Model=0xa} #define _Cortex_A76 {.ExtFamily=0xd0, .Family=0xb, .ExtModel=0x0, .Model=0xb} @@ -576,17 +580,22 @@ static void Query_DynamIQ_CMN(unsigned int cpu) ; #define _Cortex_A78AE {.ExtFamily=0xd4, .Family=0x2, .ExtModel=0x2, .Model=0x2} #define _Cortex_A78C {.ExtFamily=0xd4, .Family=0xb, .ExtModel=0x2, .Model=0x4} #define _Cortex_R82 {.ExtFamily=0xd1, .Family=0x5, .ExtModel=0x0, .Model=0x0} +#define _Cortex_R82AE {.ExtFamily=0xd1, .Family=0x4, .ExtModel=0x0, .Model=0x0} #define _Cortex_X1 {.ExtFamily=0xd4, .Family=0x4, .ExtModel=0x2, .Model=0x3} #define _Cortex_X1C {.ExtFamily=0xd4, .Family=0xc, .ExtModel=0x2, .Model=0x5} #define _Cortex_X2 {.ExtFamily=0xd4, .Family=0x8, .ExtModel=0x0, .Model=0x0} #define _Cortex_X3 {.ExtFamily=0xd4, .Family=0xe, .ExtModel=0x0, .Model=0x0} #define _Cortex_X4 {.ExtFamily=0xd8, .Family=0x2, .ExtModel=0x0, .Model=0x0} +#define _Cortex_X925 {.ExtFamily=0xd8, .Family=0x5, .ExtModel=0x0, .Model=0x0} #define _DynamIQ_DSU {.ExtFamily=0x00, .Family=0x0, .ExtModel=0x4, .Model=0x1} #define _Neoverse_E1 {.ExtFamily=0xd4, .Family=0xa, .ExtModel=0x4, .Model=0x6} #define _Neoverse_N1 {.ExtFamily=0xd0, .Family=0xc, .ExtModel=0x0, .Model=0xc} #define _Neoverse_N2 {.ExtFamily=0xd4, .Family=0x9, .ExtModel=0x0, .Model=0x0} +#define _Neoverse_N3 {.ExtFamily=0xd8, .Family=0xe, .ExtModel=0x0, .Model=0x0} #define _Neoverse_V1 {.ExtFamily=0xd4, .Family=0x0, .ExtModel=0x2, .Model=0x1} #define _Neoverse_V2 {.ExtFamily=0xd4, .Family=0xf, .ExtModel=0x0, .Model=0x0} +#define _Neoverse_V3 {.ExtFamily=0xd8, .Family=0x4, .ExtModel=0x0, .Model=0x0} +#define _Neoverse_V3AE {.ExtFamily=0xd8, .Family=0x3, .ExtModel=0x0, .Model=0x0} typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *); @@ -598,22 +607,29 @@ static char *CodeName[CODENAMES] = { [ ARM64] = "AArch64", [ ARMv8_R] = "ARMv8-R", [ ARMv8_A] = "ARMv8-A", + [ARMv8_1_A] = "ARMv8.1-A", [ARMv8_2_A] = "ARMv8.2-A", [ARMv8_3_A] = "ARMv8.3-A", [ARMv8_4_A] = "ARMv8.4-A", - [ ARMv8_5] = "ARMv8.5", - [ ARMv8_6] = "ARMv8.6", - [ ARMv8_7] = "ARMv8.7", + [ARMv8_5_A] = "ARMv8.5-A", + [ARMv8_6_A] = "ARMv8.6-A", + [ARMv8_7_A] = "ARMv8.7-A", + [ARMv8_8_A] = "ARMv8.8-A", [ ARMv9_A] = "ARMv9-A", - [ ARMv9_4] = "ARMv9.4", + [ARMv9_1_A] = "ARMv9.1-A", + [ARMv9_2_A] = "ARMv9.2-A", + [ARMv9_3_A] = "ARMv9.3-A", + [ARMv9_4_A] = "ARMv9.4-A", [ ARMv9_5] = "ARMv9.5" }; #define Arch_Misc_Processor {.Brand = ZLIST(NULL), .CN = ARM64} +#define Arch_Cortex_A320 {.Brand = ZLIST("Cortex-A320"), .CN = ARMv9_2_A} #define Arch_Cortex_A34 {.Brand = ZLIST("Cortex-A34"), .CN = ARMv8_A} #define Arch_Cortex_A35 {.Brand = ZLIST("Cortex-A35"), .CN = ARMv8_A} #define Arch_Cortex_A510 {.Brand = ZLIST("Cortex-A510"), .CN = ARMv9_A} #define Arch_Cortex_A520 {.Brand = ZLIST("Cortex-A520"), .CN = ARMv9_A} +#define Arch_Cortex_A520AE {.Brand = ZLIST("Cortex-A520AE"), .CN = ARMv9_2_A} #define Arch_Cortex_A53 {.Brand = ZLIST("Cortex-A53"), .CN = ARMv8_A} #define Arch_Cortex_A55 {.Brand = ZLIST("Cortex-A55"), .CN = ARMv8_2_A} #define Arch_Cortex_A57 {.Brand = ZLIST("Cortex-A57"), .CN = ARMv8_A} @@ -623,6 +639,8 @@ static char *CodeName[CODENAMES] = { #define Arch_Cortex_A715 {.Brand = ZLIST("Cortex-A715"), .CN = ARMv9_A} #define Arch_Cortex_A72 {.Brand = ZLIST("Cortex-A72"), .CN = ARMv8_A} #define Arch_Cortex_A720 {.Brand = ZLIST("Cortex-A720"), .CN = ARMv9_A} +#define Arch_Cortex_A720AE {.Brand = ZLIST("Cortex-A720AE"), .CN = ARMv9_2_A} +#define Arch_Cortex_A725 {.Brand = ZLIST("Cortex-A725"), .CN = ARMv9_2_A} #define Arch_Cortex_A73 {.Brand = ZLIST("Cortex-A73"), .CN = ARMv8_A} #define Arch_Cortex_A75 {.Brand = ZLIST("Cortex-A75"), .CN = ARMv8_2_A} #define Arch_Cortex_A76 {.Brand = ZLIST("Cortex-A76"), .CN = ARMv8_2_A} @@ -632,17 +650,22 @@ static char *CodeName[CODENAMES] = { #define Arch_Cortex_A78AE {.Brand = ZLIST("Cortex-A78AE"), .CN = ARMv8_2_A} #define Arch_Cortex_A78C {.Brand = ZLIST("Cortex-A78C"), .CN = ARMv8_2_A} #define Arch_Cortex_R82 {.Brand = ZLIST("Cortex-R82"), .CN = ARMv8_R} +#define Arch_Cortex_R82AE {.Brand = ZLIST("Cortex-R82AE"), .CN = ARMv8_R} #define Arch_Cortex_X1 {.Brand = ZLIST("Cortex-X1"), .CN = ARMv8_2_A} #define Arch_Cortex_X1C {.Brand = ZLIST("Cortex-X1C"), .CN = ARMv8_2_A} #define Arch_Cortex_X2 {.Brand = ZLIST("Cortex-X2"), .CN = ARMv9_A} #define Arch_Cortex_X3 {.Brand = ZLIST("Cortex-X3"), .CN = ARMv9_A} -#define Arch_Cortex_X4 {.Brand = ZLIST("Cortex-X4"), .CN = ARMv9_A} +#define Arch_Cortex_X4 {.Brand = ZLIST("Cortex-X4"), .CN = ARMv9_2_A} +#define Arch_Cortex_X925 {.Brand = ZLIST("Cortex-X925"), .CN = ARMv9_2_A} #define Arch_DynamIQ_DSU {.Brand = ZLIST("DynamIQ DSU"), .CN = ARMv8_2_A} #define Arch_Neoverse_E1 {.Brand = ZLIST("Neoverse E1"), .CN = ARMv8_2_A} #define Arch_Neoverse_N1 {.Brand = ZLIST("Neoverse N1"), .CN = ARMv8_2_A} #define Arch_Neoverse_N2 {.Brand = ZLIST("Neoverse N2"), .CN = ARMv9_A} +#define Arch_Neoverse_N3 {.Brand = ZLIST("Neoverse N3"), .CN = ARMv9_2_A} #define Arch_Neoverse_V1 {.Brand = ZLIST("Neoverse V1"), .CN = ARMv8_4_A} #define Arch_Neoverse_V2 {.Brand = ZLIST("Neoverse V2"), .CN = ARMv9_A} +#define Arch_Neoverse_V3 {.Brand = ZLIST("Neoverse V3"), .CN = ARMv9_2_A} +#define Arch_Neoverse_V3AE {.Brand = ZLIST("Neoverse V3AE"), .CN = ARMv9_2_A} static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = { {0} @@ -709,6 +732,34 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Misc_Processor }, +[Cortex_A320] = { + .Signature = _Cortex_A320, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A320 + }, [Cortex_A34] = { .Signature = _Cortex_A34, .Query = Query_GenericMachine, @@ -821,6 +872,34 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Cortex_A520 }, +[Cortex_A520AE] = { + .Signature = _Cortex_A520AE, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A520AE + }, [Cortex_A53] = { .Signature = _Cortex_A53, .Query = Query_GenericMachine, @@ -1073,6 +1152,62 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Cortex_A720 }, +[Cortex_A720AE] = { + .Signature = _Cortex_A720AE, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A720AE + }, +[Cortex_A725] = { + .Signature = _Cortex_A725, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_A725 + }, [Cortex_A73] = { .Signature = _Cortex_A73, .Query = Query_GenericMachine, @@ -1299,7 +1434,7 @@ static ARCH Arch[ARCHITECTURES] = { }, [Cortex_R82] = { .Signature = _Cortex_R82, - .Query = Query_DynamIQ, + .Query = Query_GenericMachine, .Update = PerCore_GenericMachine, .Start = Start_GenericMachine, .Stop = Stop_GenericMachine, @@ -1325,6 +1460,34 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Cortex_R82 }, +[Cortex_R82AE] = { + .Signature = _Cortex_R82AE, + .Query = Query_GenericMachine, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_R82AE + }, [Cortex_X1] = { .Signature = _Cortex_X1, .Query = Query_DynamIQ, @@ -1465,6 +1628,34 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Cortex_X4 }, +[Cortex_X925] = { + .Signature = _Cortex_X925, + .Query = Query_DynamIQ, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Cortex_X925 + }, [DynamIQ_DSU] = { .Signature = _DynamIQ_DSU, .Query = Query_GenericMachine, @@ -1577,6 +1768,34 @@ static ARCH Arch[ARCHITECTURES] = { .SystemDriver = VOID_Driver, .Architecture = Arch_Neoverse_N2 }, +[Neoverse_N3] = { + .Signature = _Neoverse_N3, + .Query = Query_DynamIQ_CMN, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_N3 + }, [Neoverse_V1] = { .Signature = _Neoverse_V1, .Query = Query_DynamIQ_CMN, @@ -1632,5 +1851,61 @@ static ARCH Arch[ARCHITECTURES] = { .Specific = Misc_Specific_Processor, .SystemDriver = VOID_Driver, .Architecture = Arch_Neoverse_V2 + }, +[Neoverse_V3] = { + .Signature = _Neoverse_V3, + .Query = Query_DynamIQ_CMN, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_V3 + }, +[Neoverse_V3AE] = { + .Signature = _Neoverse_V3AE, + .Query = Query_DynamIQ_CMN, + .Update = PerCore_GenericMachine, + .Start = Start_GenericMachine, + .Stop = Stop_GenericMachine, + .Exit = NULL, + .Timer = InitTimer_GenericMachine, + .BaseClock = BaseClock_GenericMachine, + .ClockMod = NULL, + .TurboClock = NULL, + .thermalFormula = THERMAL_FORMULA_NONE, +#ifdef CONFIG_PM_OPP + .voltageFormula = VOLTAGE_FORMULA_OPP, +#else + .voltageFormula = VOLTAGE_FORMULA_NONE, +#endif + .powerFormula = POWER_FORMULA_NONE, + .PCI_ids = PCI_Void_ids, + .Uncore = { + .Start = NULL, + .Stop = NULL, + .ClockMod = NULL + }, + .Specific = Misc_Specific_Processor, + .SystemDriver = VOID_Driver, + .Architecture = Arch_Neoverse_V3AE } }; diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h index 8dd2857..991179d 100644 --- a/aarch64/coretypes.h +++ b/aarch64/coretypes.h @@ -40,23 +40,30 @@ enum CODENAME ARM64, ARMv8_R, ARMv8_A, + ARMv8_1_A, ARMv8_2_A, ARMv8_3_A, ARMv8_4_A, - ARMv8_5, - ARMv8_6, - ARMv8_7, + ARMv8_5_A, + ARMv8_6_A, + ARMv8_7_A, + ARMv8_8_A, ARMv9_A, - ARMv9_4, + ARMv9_1_A, + ARMv9_2_A, + ARMv9_3_A, + ARMv9_4_A, ARMv9_5, CODENAMES }; enum { GenuineArch = 0, + Cortex_A320, Cortex_A34, Cortex_A35, Cortex_A510, Cortex_A520, + Cortex_A520AE, Cortex_A53, Cortex_A55, Cortex_A57, @@ -66,6 +73,8 @@ enum { GenuineArch = 0, Cortex_A715, Cortex_A72, Cortex_A720, + Cortex_A720AE, + Cortex_A725, Cortex_A73, Cortex_A75, Cortex_A76, @@ -75,17 +84,22 @@ enum { GenuineArch = 0, Cortex_A78AE, Cortex_A78C, Cortex_R82, + Cortex_R82AE, Cortex_X1, Cortex_X1C, Cortex_X2, Cortex_X3, Cortex_X4, + Cortex_X925, DynamIQ_DSU, Neoverse_E1, Neoverse_N1, Neoverse_N2, + Neoverse_N3, Neoverse_V1, Neoverse_V2, + Neoverse_V3, + Neoverse_V3AE, ARCHITECTURES };