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[riscv64] Attempt to enable the Cycle and Instruction counters

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CyrIng
2025-03-04 20:21:03 +01:00
parent 592f85564d
commit 7704ea4ee2
2 changed files with 24 additions and 2 deletions
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25
riscv64/corefreqk.c
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@@ -1693,13 +1693,34 @@ static void Controller_Exit(void)
static void Generic_Core_Counters_Set(union SAVE_AREA_CORE *Save, CORE_RO *Core)
{
/*TODO*/
register unsigned long long ctr_reg;
__asm__ volatile
(
"csrr %0, scounteren"
: "=r" (Save->SCOUNTEREN)
:
: "cc", "memory"
);
ctr_reg = Save->SCOUNTEREN | 0b101;
__asm__ volatile
(
"csrw scounteren, %0"
:
: "r" (ctr_reg)
: "cc", "memory"
);
}
static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
CORE_RO *Core)
{
/*TODO*/
__asm__ volatile
(
"csrw scounteren, %0"
:
: "r" (Save->SCOUNTEREN)
: "cc", "memory"
);
}
#define Counters_Generic(Core, T) \

1
riscv64/corefreqk.h
View File

@@ -155,6 +155,7 @@ typedef struct
union SAVE_AREA_CORE {
struct
{
unsigned long long SCOUNTEREN;
};
} SaveArea;
#ifdef CONFIG_CPU_FREQ