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[aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables

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This commit is contained in:
CyrIng
2025-05-28 15:17:58 +02:00
parent 6b176cd026
commit 6b7ea15142
6 changed files with 67 additions and 67 deletions
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14
aarch64/corefreqd.c
View File

@@ -679,7 +679,7 @@ void ThermalPoint(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{ /* Technologies aggregation. */
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(LOCKLESS,
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(BUS_LOCK,
RW(Proc)->VM,
RO(Proc)->CR_Mask) != 0;
}
@@ -688,27 +688,27 @@ void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{
const unsigned short
CLRBHB = BITWISEAND_CC( LOCKLESS,
CLRBHB = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CLRBHB,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_1 = BITWISEAND_CC( LOCKLESS,
CSV2_1 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_1,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_2 = BITWISEAND_CC( LOCKLESS,
CSV2_2 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_2,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_3 = BITWISEAND_CC( LOCKLESS,
CSV2_3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV3 = BITWISEAND_CC( LOCKLESS,
CSV3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
SSBS = BITCMP_CC( LOCKLESS,
SSBS = BITCMP_CC( BUS_LOCK,
RW(Proc)->SSBS,
RO(Proc)->SPEC_CTRL_Mask );

64
aarch64/corefreqk.c
View File

@@ -2819,9 +2819,9 @@ static void SystemRegisters(CORE_RO *Core)
: "cc", "memory", "%x11", "%x12", "%x13", "%x14"
);
if (mmfr1.VH) {
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->VM, Core->Bind);
} else {
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->VM, Core->Bind);
}
Core->Query.SCTLRX = 0;
if (Experimental) {
@@ -2836,9 +2836,9 @@ static void SystemRegisters(CORE_RO *Core)
);
}
if (isar2.CLRBHB == 0b0001) {
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
} else {
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CLRBHB, Core->Bind);
}
switch (pfr0.EL3) {
case 0b0010:
@@ -2879,38 +2879,38 @@ static void SystemRegisters(CORE_RO *Core)
}
switch (pfr0.CSV2) {
case 0b0001:
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
break;
case 0b0010:
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
break;
case 0b0011:
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
break;
default:
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_1, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_2, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_3, Core->Bind);
}
if (pfr0.CSV3) {
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV3, Core->Bind);
} else {
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV3, Core->Bind);
}
if (PUBLIC(RO(Proc))->Features.SSBS == 0b0010)
{
SSBS2 mrs_ssbs = {.value = SysRegRead(MRS_SSBS2)};
if (mrs_ssbs.SSBS) {
BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RW(Proc))->SSBS, Core->Bind);
} else {
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->SSBS, Core->Bind);
}
Core->SystemRegister.FLAGS |= (1LLU << FLAG_SSBS);
}
@@ -2960,7 +2960,7 @@ static void SystemRegisters(CORE_RO *Core)
volatile unsigned long long fpmr = SysRegRead(MRS_FPMR);
UNUSED(fpmr); /*TODO*/
}
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
}
#define Pkg_Reset_ThermalPoint(Pkg) \
@@ -2972,17 +2972,17 @@ static void SystemRegisters(CORE_RO *Core)
static void PerCore_Reset(CORE_RO *Core)
{
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_1 , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_2 , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV2_3 , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->CSV3 , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->SSBS , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_1 , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_2 , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV2_3 , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->CSV3 , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->SSBS , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->VM , Core->Bind);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind);
@@ -3041,7 +3041,7 @@ static void PerCore_GenericMachine(void *arg)
SystemRegisters(Core);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 56)

14
ppc64le/corefreqd.c
View File

@@ -679,7 +679,7 @@ void ThermalPoint(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{ /* Technologies aggregation. */
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(LOCKLESS,
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(BUS_LOCK,
RW(Proc)->VM,
RO(Proc)->CR_Mask) != 0;
}
@@ -688,27 +688,27 @@ void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{
/* const unsigned short
CLRBHB = BITWISEAND_CC( LOCKLESS,
CLRBHB = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CLRBHB,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_1 = BITWISEAND_CC( LOCKLESS,
CSV2_1 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_1,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_2 = BITWISEAND_CC( LOCKLESS,
CSV2_2 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_2,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_3 = BITWISEAND_CC( LOCKLESS,
CSV2_3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV3 = BITWISEAND_CC( LOCKLESS,
CSV3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
SSBS = BITCMP_CC( LOCKLESS,
SSBS = BITCMP_CC( BUS_LOCK,
RW(Proc)->SSBS,
RO(Proc)->SPEC_CTRL_Mask );
*/

14
ppc64le/corefreqk.c
View File

@@ -1456,7 +1456,7 @@ static void SystemRegisters(CORE_RO *Core)
: "i" (0xfffffffffffffff9), "i" (0x7)
: "%14", "%15", "cc", "memory"
);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
}
#define Pkg_Reset_ThermalPoint(Pkg) \
@@ -1468,12 +1468,12 @@ static void SystemRegisters(CORE_RO *Core)
static void PerCore_Reset(CORE_RO *Core)
{
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->VM , Core->Bind);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind);
@@ -1500,7 +1500,7 @@ static void PerCore_GenericMachine(void *arg)
SystemRegisters(Core);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 56)

14
riscv64/corefreqd.c
View File

@@ -679,7 +679,7 @@ void ThermalPoint(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{ /* Technologies aggregation. */
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(LOCKLESS,
RO(Shm)->Proc.Technology.VM = BITWISEAND_CC(BUS_LOCK,
RW(Proc)->VM,
RO(Proc)->CR_Mask) != 0;
}
@@ -688,27 +688,27 @@ void Mitigation_Stage( RO(SHM_STRUCT) *RO(Shm),
RO(PROC) *RO(Proc), RW(PROC) *RW(Proc) )
{
/* const unsigned short
CLRBHB = BITWISEAND_CC( LOCKLESS,
CLRBHB = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CLRBHB,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_1 = BITWISEAND_CC( LOCKLESS,
CSV2_1 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_1,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_2 = BITWISEAND_CC( LOCKLESS,
CSV2_2 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_2,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV2_3 = BITWISEAND_CC( LOCKLESS,
CSV2_3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV2_3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
CSV3 = BITWISEAND_CC( LOCKLESS,
CSV3 = BITWISEAND_CC( BUS_LOCK,
RW(Proc)->CSV3,
RO(Proc)->SPEC_CTRL_Mask) != 0,
SSBS = BITCMP_CC( LOCKLESS,
SSBS = BITCMP_CC( BUS_LOCK,
RW(Proc)->SSBS,
RO(Proc)->SPEC_CTRL_Mask );
*/

14
riscv64/corefreqk.c
View File

@@ -1443,7 +1443,7 @@ static void SystemRegisters(CORE_RO *Core)
:
: "memory"
);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
}
#define Pkg_Reset_ThermalPoint(Pkg) \
@@ -1455,12 +1455,12 @@ static void SystemRegisters(CORE_RO *Core)
static void PerCore_Reset(CORE_RO *Core)
{
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->HWP_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->CR_Mask , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->VM , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->HWP , Core->Bind);
BITCLR_CC(BUS_LOCK, PUBLIC(RW(Proc))->VM , Core->Bind);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask);
BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind);
@@ -1487,7 +1487,7 @@ static void PerCore_GenericMachine(void *arg)
SystemRegisters(Core);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 56)