[AMD][Zen] Count DIMM ranks from the enabled chip select

This commit is contained in:
CyrIng
2025-05-14 14:33:59 +02:00
parent fcc0e0f70e
commit 398dc12544
3 changed files with 11 additions and 7 deletions

View File

@@ -664,6 +664,7 @@ typedef struct
struct {
/* 5003{0,4}h*/ AMD_ZEN_UMC_DRAM_ADDR_CFG DAC; /* 32 bits */
/* 5008{0,4}h*/ AMD_17_UMC_DIMM_CFG CFG; /* 32 bits */
unsigned short Ranks;
} AMD17h;
} DIMM[MC_MAX_DIMM];
} Channel[MC_MAX_CHA];

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@@ -6604,11 +6604,7 @@ void AMD_17h_UMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
+ RO(Proc)->Uncore.MC[mc].Channel[cha].DIMM[slot].AMD17h.DAC.NumCol);
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
RO(Proc)->Uncore.MC[mc].Channel[cha].AMD17h.CONFIG.DdrType == 0 ?
RO(Proc)->Uncore.MC[mc].Channel[cha].DIMM[
slot
].AMD17h.CFG.OnDimmMirror ? 2 : 1
: 2; /* DDR5 */
RO(Proc)->Uncore.MC[mc].Channel[cha].DIMM[slot].AMD17h.Ranks;
DIMM_Size = 8LLU;
DIMM_Size *= RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks;

View File

@@ -6936,8 +6936,8 @@ static void AMD_Zen_UMC(struct pci_dev *dev,
[1] = UMC_BAR + CS_MASK[1][1]
}
};
unsigned short chip;
for (chip = 0; chip < 4; chip++)
unsigned short chip, ranks = 0;
for (chip = 0; chip < MC_MAX_DIMM; chip++)
{
const unsigned short slot = chip & 1;
unsigned short sec;
@@ -6965,8 +6965,15 @@ static void AMD_Zen_UMC(struct pci_dev *dev,
Core_AMD_SMN_Read(PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha]\
.AMD17h.CHIP[chip][sec].Chip,
addr[0], dev );
ranks += BITVAL(PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha]\
.AMD17h.CHIP[chip][sec].Chip.value, 0);
}
}
for (chip = 0; chip < MC_MAX_DIMM; chip++) {
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].DIMM[chip].AMD17h.Ranks = \
ranks;
}
Core_AMD_SMN_Read(PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].AMD17h.CONFIG,
UMC_BAR + 0x100, dev );