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[aarch64] If FEAT_CCIDX implemented read NumSets from upper reg

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CyrIng
2025-03-19 17:26:50 +01:00
parent d54e1b8c56
commit 33b50d0a2b
3 changed files with 10 additions and 2 deletions
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4
aarch64/corefreq-api.h
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@@ -46,7 +46,9 @@ typedef struct
RdAlloc : 30-29, RdAlloc : 30-29,
WrBack : 31-30, WrBack : 31-30,
WrThrough : 32-31, WrThrough : 32-31,
RES0 : 64-32; NumSets : 56-32,
RES0 : 63-56,
FEAT_CCIDX : 64-63;
}; };
} ccsid; } ccsid;
unsigned int Size; unsigned int Size;

4
aarch64/corefreqd.c
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@@ -789,7 +789,9 @@ void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core),
RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSz + 4; RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSz + 4;
RO(Shm)->Cpu[cpu].Topology.Cache[level].Set = \ RO(Shm)->Cpu[cpu].Topology.Cache[level].Set = \
RO(Core, AT(cpu))->T.Cache[level].ccsid.Set + 1; RO(Core, AT(cpu))->T.Cache[level].ccsid.FEAT_CCIDX ?
RO(Core, AT(cpu))->T.Cache[level].ccsid.NumSets + 1
: RO(Core, AT(cpu))->T.Cache[level].ccsid.Set + 1;
RO(Shm)->Cpu[cpu].Topology.Cache[level].Way = \ RO(Shm)->Cpu[cpu].Topology.Cache[level].Way = \
RO(Core, AT(cpu))->T.Cache[level].ccsid.Assoc + 1; RO(Core, AT(cpu))->T.Cache[level].ccsid.Assoc + 1;

4
aarch64/corefreqk.c
View File

@@ -2067,6 +2067,8 @@ static void Cache_Level(CORE_RO *Core, unsigned int level, unsigned int select)
[2] = { .InD = 0, .Level = 1 }, /* L2 */ [2] = { .InD = 0, .Level = 1 }, /* L2 */
[3] = { .InD = 0, .Level = 2 } /* L3 */ [3] = { .InD = 0, .Level = 2 } /* L3 */
}; };
volatile AA64MMFR2 mmfr2;
__asm__ volatile __asm__ volatile
( (
"msr csselr_el1, %[cssel]" "\n\t" "msr csselr_el1, %[cssel]" "\n\t"
@@ -2076,6 +2078,8 @@ static void Cache_Level(CORE_RO *Core, unsigned int level, unsigned int select)
: [cssel] "r" (cssel[select]) : [cssel] "r" (cssel[select])
: "memory" : "memory"
); );
mmfr2.value = SysRegRead(ID_AA64MMFR2_EL1);
Core->T.Cache[level].ccsid.FEAT_CCIDX = mmfr2.CCIDX == 0b0001 ? 1 : 0;
} }
static void Cache_Topology(CORE_RO *Core) static void Cache_Topology(CORE_RO *Core)